Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh

- R8A774A1 / Beacon EmbeddedWorks RZG2M Dev Kit support

3 files changed, 187 insertions, 0 deletions

diff --git a/include/configs/beacon-rzg2m.h b/include/configs/beacon-rzg2m.h
new file mode 100644
index 0000000000..0e48fbd46e
--- /dev/null
+++ b/include/configs/beacon-rzg2m.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Compass Electronics Group, LLC
+ */
+
+#ifndef __BEACON_RZG2M_H
+#define __BEACON_RZG2M_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII_MULTI
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+/* #define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE) */
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"usb_pgood_delay=2000\0"	\
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"console=ttySC0,115200\0" \
+	"fdt_addr=0x48000000\0" \
+	"loadaddr=0x48080000\0" \
+	"boot_fdt=try\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcrootpart=2\0" \
+	"finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+	" root=PARTUUID=${uuid} rootwait rw ${optargs}\0" \
+	"loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run finduuid; run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+	   "if run loadbootscript; then " \
+		   "run bootscript; " \
+	   "else " \
+		   "if run loadimage; then " \
+			   "run mmcboot; " \
+		   "else run netboot; " \
+		   "fi; " \
+	   "fi; " \
+	"else booti ${loadaddr} - ${fdt_addr}; fi"
+
+#endif /* __BEACON_RZG2M_H */
diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
new file mode 100644
index 0000000000..ac3fde148c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a774a1 CPG Core Clocks */
+#define R8A774A1_CLK_Z			0
+#define R8A774A1_CLK_Z2			1
+#define R8A774A1_CLK_ZR			2
+#define R8A774A1_CLK_ZG			3
+#define R8A774A1_CLK_ZTR		4
+#define R8A774A1_CLK_ZTRD2		5
+#define R8A774A1_CLK_ZT			6
+#define R8A774A1_CLK_ZX			7
+#define R8A774A1_CLK_S0D1		8
+#define R8A774A1_CLK_S0D2		9
+#define R8A774A1_CLK_S0D3		10
+#define R8A774A1_CLK_S0D4		11
+#define R8A774A1_CLK_S0D6		12
+#define R8A774A1_CLK_S0D8		13
+#define R8A774A1_CLK_S0D12		14
+#define R8A774A1_CLK_S1D1		15
+#define R8A774A1_CLK_S1D2		16
+#define R8A774A1_CLK_S1D4		17
+#define R8A774A1_CLK_S2D1		18
+#define R8A774A1_CLK_S2D2		19
+#define R8A774A1_CLK_S2D4		20
+#define R8A774A1_CLK_S3D1		21
+#define R8A774A1_CLK_S3D2		22
+#define R8A774A1_CLK_S3D4		23
+#define R8A774A1_CLK_LB			24
+#define R8A774A1_CLK_CL			25
+#define R8A774A1_CLK_ZB3		26
+#define R8A774A1_CLK_ZB3D2		27
+#define R8A774A1_CLK_ZB3D4		28
+#define R8A774A1_CLK_CR			29
+#define R8A774A1_CLK_CRD2		30
+#define R8A774A1_CLK_SD0H		31
+#define R8A774A1_CLK_SD0		32
+#define R8A774A1_CLK_SD1H		33
+#define R8A774A1_CLK_SD1		34
+#define R8A774A1_CLK_SD2H		35
+#define R8A774A1_CLK_SD2		36
+#define R8A774A1_CLK_SD3H		37
+#define R8A774A1_CLK_SD3		38
+#define R8A774A1_CLK_SSP2		39
+#define R8A774A1_CLK_SSP1		40
+#define R8A774A1_CLK_SSPRS		41
+#define R8A774A1_CLK_RPC		42
+#define R8A774A1_CLK_RPCD2		43
+#define R8A774A1_CLK_MSO		44
+#define R8A774A1_CLK_CANFD		45
+#define R8A774A1_CLK_HDMI		46
+#define R8A774A1_CLK_CSI0		47
+#define R8A774A1_CLK_CSIREF		48
+#define R8A774A1_CLK_CP			49
+#define R8A774A1_CLK_CPEX		50
+#define R8A774A1_CLK_R			51
+#define R8A774A1_CLK_OSC		52
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h
new file mode 100644
index 0000000000..d84ea0eb12
--- /dev/null
+++ b/include/dt-bindings/power/r8a774a1-sysc.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774A1_PD_CA57_CPU0		 0
+#define R8A774A1_PD_CA57_CPU1		 1
+#define R8A774A1_PD_CA53_CPU0		 5
+#define R8A774A1_PD_CA53_CPU1		 6
+#define R8A774A1_PD_CA53_CPU2		 7
+#define R8A774A1_PD_CA53_CPU3		 8
+#define R8A774A1_PD_CA57_SCU		12
+#define R8A774A1_PD_CR7			13
+#define R8A774A1_PD_A3VC		14
+#define R8A774A1_PD_3DG_A		17
+#define R8A774A1_PD_3DG_B		18
+#define R8A774A1_PD_CA53_SCU		21
+#define R8A774A1_PD_A3IR		24
+#define R8A774A1_PD_A2VC0		25
+#define R8A774A1_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A774A1_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */