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| author | Michal Simek <michal.simek@xilinx.com> | 2016-10-18 16:10:25 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-11-15 15:28:04 +0100 |
| commit | 05c59d0bc83f28888e5f2cc11b679a721605a46b (patch) | |
| tree | 4aadd7bff15ec498350cbc6e785002058f86f355 /include/zynqpl.h | |
| parent | 4eaf8f5424ccfc2c285a70b9a337e5b39d9e39e7 (diff) | |
| download | u-boot-05c59d0bc83f28888e5f2cc11b679a721605a46b.tar.gz u-boot-05c59d0bc83f28888e5f2cc11b679a721605a46b.tar.xz u-boot-05c59d0bc83f28888e5f2cc11b679a721605a46b.zip | |
ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devices
Zynq 7000S (Single A9 core) devices is using different ID code.
This patch adds this new codes and assign them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'include/zynqpl.h')
| -rw-r--r-- | include/zynqpl.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/zynqpl.h b/include/zynqpl.h index 1d37a51a04..5a34a17dae 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -19,7 +19,10 @@ extern struct xilinx_fpga_op zynq_op; # define FPGA_ZYNQPL_OPS NULL #endif +#define XILINX_ZYNQ_7007S 0x3 #define XILINX_ZYNQ_7010 0x2 +#define XILINX_ZYNQ_7012S 0x1c +#define XILINX_ZYNQ_7014S 0x8 #define XILINX_ZYNQ_7015 0x1b #define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7030 0xc @@ -28,7 +31,10 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_ZYNQ_7100 0x16 /* Device Image Sizes */ +#define XILINX_XC7Z007S_SIZE 16669920/8 #define XILINX_XC7Z010_SIZE 16669920/8 +#define XILINX_XC7Z012S_SIZE 28085344/8 +#define XILINX_XC7Z014S_SIZE 32364512/8 #define XILINX_XC7Z015_SIZE 28085344/8 #define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z030_SIZE 47839328/8 @@ -37,10 +43,22 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_XC7Z100_SIZE 139330784/8 /* Descriptor Macros */ +#define XILINX_XC7Z007S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z007s" } + #define XILINX_XC7Z010_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ "7z010" } +#define XILINX_XC7Z012S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z012s" } + +#define XILINX_XC7Z014S_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ + "7z014s" } + #define XILINX_XC7Z015_DESC(cookie) \ { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ "7z015" } |