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| author | Tom Rini <trini@konsulko.com> | 2021-04-09 13:10:38 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-04-09 13:10:38 -0400 |
| commit | 92c4eb7ae3e8fe2c2b3c5b37f882b42282a08e84 (patch) | |
| tree | 2ce9a497994386b4f58861107a792fe69b82577e /include/linux | |
| parent | a1e95e3805eacca1162f6049dceb9b1d2726cbf5 (diff) | |
| parent | 96fe4f6485e92ed9da464c96c5f536698c5ee66d (diff) | |
| download | u-boot-92c4eb7ae3e8fe2c2b3c5b37f882b42282a08e84.tar.gz u-boot-92c4eb7ae3e8fe2c2b3c5b37f882b42282a08e84.tar.xz u-boot-92c4eb7ae3e8fe2c2b3c5b37f882b42282a08e84.zip | |
Merge branch 'v2021.07-rc1' of https://github.com/lftan/u-boot
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/intel-smc.h | 52 |
1 files changed, 9 insertions, 43 deletions
diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index cacb410691..a54eff43ad 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -519,55 +519,21 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD) /* - * Request INTEL_SIP_SMC_HPS_SET_PHYINTF + * Request INTEL_SIP_SMC_GET_USERCODE * - * Select EMACx PHY interface + * Send mailbox command to get usercode from SDM * * Call register usage: - * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF - * a1 EMAC number: - * 0 - EMAC0 - * 1 - EMAC1 - * 2 - EMAC2 - * a2 Type of PHY interface: - * 0 - GMII_MII - * 1 - RGMII - * 2 - RMII - * 3 - RESET - * a3-7 not used + * a0 INTEL_SIP_SMC_GET_USERCODE + * a1-7 not used. * * Return status * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR + * a1 User code + * a2-3 not used. */ -#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61 -#define INTEL_SIP_SMC_HPS_SET_PHYINTF \ - INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF) - -/* - * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK - * - * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC - * - * Call register usage: - * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK - * a1 Select which phase shift of the clock for cclk_in_drv (drvsel): - * 0 - 0 degree - * 1 - 45 degrees - * 2 - 90 degrees - * 3 - 135 degrees - * 4 - 180 degrees - * 5 - 225 degrees - * 6 - 270 degrees - * 7 - 315 degrees - * a2 Select which phase shift of the clock for cclk_in_sample (smplsel): - * (Same as above) - * a3-7 not used - * - * Return status - * a0 INTEL_SIP_SMC_STATUS_OK - */ -#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62 -#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \ - INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK) +#define INTEL_SIP_SMC_FUNCID_GET_USERCODE 61 +#define INTEL_SIP_SMC_GET_USERCODE \ + INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_GET_USERCODE) #endif |