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authorBin Meng <bmeng.cn@gmail.com>2015-05-25 22:35:04 +0800
committerSimon Glass <sjg@chromium.org>2015-06-04 02:39:39 -0600
commit9c7dea602edd9027848d312e9b3b69f06c15f163 (patch)
tree4893732c170a3a889b819482f7003491ecbac11c /include/dt-bindings/interrupt-router
parent2aa3a7fb1c24afd4c0e12360acccf3234d8fe019 (diff)
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x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include/dt-bindings/interrupt-router')
-rw-r--r--include/dt-bindings/interrupt-router/intel-irq.h31
1 files changed, 31 insertions, 0 deletions
diff --git a/include/dt-bindings/interrupt-router/intel-irq.h b/include/dt-bindings/interrupt-router/intel-irq.h
new file mode 100644
index 0000000000..5092f33dfa
--- /dev/null
+++ b/include/dt-bindings/interrupt-router/intel-irq.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_INTEL_IRQ_H_
+#define _DT_BINDINGS_INTEL_IRQ_H_
+
+/* PCI interrupt pin */
+#define INTA 1
+#define INTB 2
+#define INTC 3
+#define INTD 4
+
+/* PIRQs */
+#define PIRQA 0
+#define PIRQB 1
+#define PIRQC 2
+#define PIRQD 3
+#define PIRQE 4
+#define PIRQF 5
+#define PIRQG 6
+#define PIRQH 7
+
+/* PCI bdf encoding */
+#ifndef PCI_BDF
+#define PCI_BDF(b, d, f) ((b) << 16 | (d) << 11 | (f) << 8)
+#endif
+
+#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */