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| author | Adam Ford <aford173@gmail.com> | 2020-06-30 09:30:07 -0500 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2020-07-25 11:16:39 +0200 |
| commit | 3aabb0c3f17309c802be28d8417b19d04b85976c (patch) | |
| tree | d126f594013b8df8d104be90d0659b864aa3b10a /include/dt-bindings/clock | |
| parent | dbabfcc8734c071a4efcaf8eac7cb641fa0ed9b9 (diff) | |
| download | u-boot-3aabb0c3f17309c802be28d8417b19d04b85976c.tar.gz u-boot-3aabb0c3f17309c802be28d8417b19d04b85976c.tar.xz u-boot-3aabb0c3f17309c802be28d8417b19d04b85976c.zip | |
ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1
This patch imports the device tree and required bindings to permit
the device tree to build for the R8Z774A1 (RZ/G2M).
Signed-off-by: Adam Ford <aford173@gmail.com>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h new file mode 100644 index 0000000000..ac3fde148c --- /dev/null +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a774a1 CPG Core Clocks */ +#define R8A774A1_CLK_Z 0 +#define R8A774A1_CLK_Z2 1 +#define R8A774A1_CLK_ZR 2 +#define R8A774A1_CLK_ZG 3 +#define R8A774A1_CLK_ZTR 4 +#define R8A774A1_CLK_ZTRD2 5 +#define R8A774A1_CLK_ZT 6 +#define R8A774A1_CLK_ZX 7 +#define R8A774A1_CLK_S0D1 8 +#define R8A774A1_CLK_S0D2 9 +#define R8A774A1_CLK_S0D3 10 +#define R8A774A1_CLK_S0D4 11 +#define R8A774A1_CLK_S0D6 12 +#define R8A774A1_CLK_S0D8 13 +#define R8A774A1_CLK_S0D12 14 +#define R8A774A1_CLK_S1D1 15 +#define R8A774A1_CLK_S1D2 16 +#define R8A774A1_CLK_S1D4 17 +#define R8A774A1_CLK_S2D1 18 +#define R8A774A1_CLK_S2D2 19 +#define R8A774A1_CLK_S2D4 20 +#define R8A774A1_CLK_S3D1 21 +#define R8A774A1_CLK_S3D2 22 +#define R8A774A1_CLK_S3D4 23 +#define R8A774A1_CLK_LB 24 +#define R8A774A1_CLK_CL 25 +#define R8A774A1_CLK_ZB3 26 +#define R8A774A1_CLK_ZB3D2 27 +#define R8A774A1_CLK_ZB3D4 28 +#define R8A774A1_CLK_CR 29 +#define R8A774A1_CLK_CRD2 30 +#define R8A774A1_CLK_SD0H 31 +#define R8A774A1_CLK_SD0 32 +#define R8A774A1_CLK_SD1H 33 +#define R8A774A1_CLK_SD1 34 +#define R8A774A1_CLK_SD2H 35 +#define R8A774A1_CLK_SD2 36 +#define R8A774A1_CLK_SD3H 37 +#define R8A774A1_CLK_SD3 38 +#define R8A774A1_CLK_SSP2 39 +#define R8A774A1_CLK_SSP1 40 +#define R8A774A1_CLK_SSPRS 41 +#define R8A774A1_CLK_RPC 42 +#define R8A774A1_CLK_RPCD2 43 +#define R8A774A1_CLK_MSO 44 +#define R8A774A1_CLK_CANFD 45 +#define R8A774A1_CLK_HDMI 46 +#define R8A774A1_CLK_CSI0 47 +#define R8A774A1_CLK_CSIREF 48 +#define R8A774A1_CLK_CP 49 +#define R8A774A1_CLK_CPEX 50 +#define R8A774A1_CLK_R 51 +#define R8A774A1_CLK_OSC 52 + +#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ |