diff options
author | Padmarao Begari <padmarao.begari@microchip.com> | 2021-01-15 08:20:38 +0530 |
---|---|---|
committer | Andes <uboot@andestech.com> | 2021-01-18 11:06:38 +0800 |
commit | 2f27c9219e45c8abcbd53b0e66eff1f5bcae7c7e (patch) | |
tree | e959e5d54e3f668459f042484352af2d2adfb54a /include/dt-bindings/clock/microchip-mpfs-clock.h | |
parent | 1b4593826cdb00e7737969e7c8603accb874cd5b (diff) | |
download | u-boot-2f27c9219e45c8abcbd53b0e66eff1f5bcae7c7e.tar.gz u-boot-2f27c9219e45c8abcbd53b0e66eff1f5bcae7c7e.tar.xz u-boot-2f27c9219e45c8abcbd53b0e66eff1f5bcae7c7e.zip |
clk: Add Microchip PolarFire SoC clock driver
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Diffstat (limited to 'include/dt-bindings/clock/microchip-mpfs-clock.h')
-rw-r--r-- | include/dt-bindings/clock/microchip-mpfs-clock.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h new file mode 100644 index 0000000000..55fe64693f --- /dev/null +++ b/include/dt-bindings/clock/microchip-mpfs-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ + +#define CLK_CPU 0 +#define CLK_AXI 1 +#define CLK_AHB 2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC 6 +#define CLK_TIMER 7 +#define CLK_MMUART0 8 +#define CLK_MMUART1 9 +#define CLK_MMUART2 10 +#define CLK_MMUART3 11 +#define CLK_MMUART4 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB 19 +#define CLK_RESERVED 20 +#define CLK_RTC 21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM 32 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ |