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| author | Andy Yan <andy.yan@rock-chips.com> | 2019-11-14 11:21:12 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-11-17 17:22:53 +0800 |
| commit | f1a225229a64168fa489b5f8c82264f1857f6b60 (patch) | |
| tree | d9d1d9cbc60e358395429105aa6efd7d78d28f72 /include/configs | |
| parent | bbda2ed5840c67758fb172fbcdd6398f6ab5fe25 (diff) | |
| download | u-boot-f1a225229a64168fa489b5f8c82264f1857f6b60.tar.gz u-boot-f1a225229a64168fa489b5f8c82264f1857f6b60.tar.xz u-boot-f1a225229a64168fa489b5f8c82264f1857f6b60.zip | |
arm: rockchip: Add RK3308 SOC support
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/rk3308_common.h | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h new file mode 100644 index 0000000000..a67d3d7d1b --- /dev/null +++ b/include/configs/rk3308_common.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#ifndef __CONFIG_RK3308_COMMON_H +#define __CONFIG_RK3308_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SPL_MAX_SIZE 0x20000 +#define CONFIG_SPL_BSS_START_ADDR 0x00400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 +#define CONFIG_IRAM_BASE 0xfff80000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00800000 +#define CONFIG_SYS_LOAD_ADDR 0x00C00800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define COUNTER_FREQUENCY 24000000 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 +#define SDRAM_BANK_SIZE (2UL << 30) + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x01f00000\0" \ + "kernel_addr_r=0x00680000\0" \ + "ramdisk_addr_r=0x04000000\0" + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif + +#endif |