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| author | Marek Vasut <marex@denx.de> | 2020-02-15 14:10:02 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-03-01 22:07:32 +0100 |
| commit | c808ab472aa20a4646a4980951d2b067df2c49c2 (patch) | |
| tree | 261b5da97fd5f519220b94229e5650721d0c7810 /include/configs/socfpga_common.h | |
| parent | b371acccadf3dd800dedf3c8839abfeb8939b8d6 (diff) | |
| download | u-boot-c808ab472aa20a4646a4980951d2b067df2c49c2.tar.gz u-boot-c808ab472aa20a4646a4980951d2b067df2c49c2.tar.xz u-boot-c808ab472aa20a4646a4980951d2b067df2c49c2.zip | |
ARM: socfpga: Permit overriding the default timer frequency
The default timer rate may be different than 25 MHz, permit overriding
the default rate in board configuration file. Ultimatelly, this should
be properly handled by a clock driver, however that is not available
on Gen5 yet.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'include/configs/socfpga_common.h')
| -rw-r--r-- | include/configs/socfpga_common.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8d10469e7c..54a43569dc 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -94,12 +94,13 @@ * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) +#ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 #endif +#endif /* * L4 Watchdog |