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authorKever Yang <kever.yang@rock-chips.com>2019-10-18 15:54:16 +0800
committerKever Yang <kever.yang@rock-chips.com>2019-11-10 20:40:20 +0800
commit6024467bcc0e38fb5f1d2d80b73e770c94e4530c (patch)
tree585fb3a3eba902fce52687f7e8c224f3d7228c20 /include/configs/rk3368_common.h
parent006ab58d4636124f617174fa2dfe24739874ee91 (diff)
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rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs
Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to limit the SPL size in 0x40000(start from 0) so that we don't need to do the relocate for ATF loading. Note that there will be separate BSS, STACK and MALLOC heap, so the size 0x40000(256KB) should be enough for SPL text. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'include/configs/rk3368_common.h')
-rw-r--r--include/configs/rk3368_common.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index e4b2114a0d..e57d0efa7f 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -27,7 +27,7 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00280000
-#define CONFIG_SPL_MAX_SIZE 0x60000
+#define CONFIG_SPL_MAX_SIZE 0x40000
#define CONFIG_SPL_BSS_START_ADDR 0x400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
#define CONFIG_SPL_STACK 0x00188000