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authorTom Rini <trini@konsulko.com>2020-06-25 09:33:39 -0400
committerTom Rini <trini@konsulko.com>2020-06-25 09:33:39 -0400
commitf0e236c8d6646f6ef0ebf8f043962a07dda3b3a3 (patch)
tree393f3a5a757c2faf8e1506a6a94e70d253b591dd /include/configs/lacie_kw.h
parent6ccbd1590fb15b673c90c9ccde5da8dcaaf80a10 (diff)
parentb8fd54d62f92658cbd20ca051304e13eabf24ddd (diff)
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Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.10 Versal: - xspi bootmode fix - Removing one clock from clk driver - Align u-boot memory setting with OS by default - Map TCM and OCM by default ZynqMP: - Minor DT improvements - Reduce console buffer for mini configurations - Add fix for AMS - Add support for XDP platform Zynq: - Support for AES engine - Enable bigger memory test by default - Extend documentation for SD preparation - Use different freq for Topic miami board mmc: - minor GD pointer removal net: - Support fixed-link cases by zynq gem - Fix phy looking loop in axi enet driver spi: - Cleanup global macros for xilinx spi drivers firmware: - Add support for pmufw reloading fpga: - Improve error status reporting common: - Remove 4kB addition space for FDT allocation
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