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authorMario Six <mario.six@gdsys.cc>2019-01-21 09:18:03 +0100
committerMario Six <mario.six@gdsys.cc>2019-05-21 07:52:33 +0200
commitfe7d654d04a4ba87813dcf8acb7a17373029770d (patch)
treeacff08e60a356274b602f42d44a975b7a279eca2 /include/configs/kmcoge5ne.h
parentdaac2086ce1a36ffbd603eb643f45d14faae40e7 (diff)
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mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig
Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/kmcoge5ne.h')
-rw-r--r--include/configs/kmcoge5ne.h12
1 files changed, 0 insertions, 12 deletions
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
index 5027073d6e..ede8ae6ba5 100644
--- a/include/configs/kmcoge5ne.h
+++ b/include/configs/kmcoge5ne.h
@@ -108,9 +108,6 @@
*/
#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
-/* FLASH */
-#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
@@ -120,9 +117,6 @@
* PRIO1/PIGGY on the local bus CS1
*/
-/* KMBEC_FPGA */
-#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/*
* Serial Port
@@ -336,9 +330,6 @@
#define CONFIG_SYS_PAXE_BASE 0xA0000000
#define CONFIG_SYS_PAXE_SIZE 256
-/* PAXE */
-#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/*
* BFTIC3 on the local bus CS4
@@ -346,9 +337,6 @@
#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
#define CONFIG_SYS_BFTIC3_SIZE 256
-/* BFTIC3 */
-#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/* enable POST tests */
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)