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author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 09:18:16 +0100 |
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committer | Mario Six <mario.six@gdsys.cc> | 2019-05-21 07:52:33 +0200 |
commit | 133ec602846d28a7915a7b3149d05d1c8a270873 (patch) | |
tree | 507157ce06ed8113cb03196d664e5d28eecac486 /include/configs/caddy2.h | |
parent | 8a81bfd271f9122933c865c790780024f5e2d576 (diff) | |
download | u-boot-133ec602846d28a7915a7b3149d05d1c8a270873.tar.gz u-boot-133ec602846d28a7915a7b3149d05d1c8a270873.tar.xz u-boot-133ec602846d28a7915a7b3149d05d1c8a270873.zip |
mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE
CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/caddy2.h')
-rw-r--r-- | include/configs/caddy2.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index f14e5faafa..928136f325 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -52,7 +52,6 @@ #undef CONFIG_DDR_32BIT #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING |