sh: First support code of SuperH.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

13 files changed, 1294 insertions, 0 deletions

diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h
new file mode 100644
index 0000000000..44dca9ff68
--- /dev/null
+++ b/include/asm-sh/bitops.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SH_BITOPS_H_
+#define __ASM_SH_BITOPS_H_
+
+extern void set_bit(int nr, volatile void * a);
+extern void clear_bit(int nr, volatile void * a);
+extern int test_and_clear_bit(int nr, volatile void * a);
+extern void change_bit(unsigned long nr, volatile void *addr);
+extern int test_and_set_bit(int nr, volatile void * a);
+extern int test_and_change_bit(int nr, volatile void * addr);
+extern int test_bit(int nr, volatile void * a);
+extern int ffs(int i);
+
+#endif
diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h
new file mode 100644
index 0000000000..8836e657de
--- /dev/null
+++ b/include/asm-sh/byteorder.h
@@ -0,0 +1,31 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_SH_BYTEORDER_H_
+#define __ASM_SH_BYTEORDER_H_
+
+#include <config.h>
+#include <asm/types.h>
+
+#ifdef __LITTLE_ENDIAN__
+#include <linux/byteorder/little_endian.h>
+#else
+#include <linux/byteorder/big_endian.h>
+#endif
+
+#endif
+
diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h
new file mode 100644
index 0000000000..e0275f32a0
--- /dev/null
+++ b/include/asm-sh/cpu_sh4.h
@@ -0,0 +1,10 @@
+#ifndef _ASM_CPU_SH4_H_
+#define _ASM_CPU_SH4_H_
+#if defined (CONFIG_CPU_SH7750)
+#include <asm/cpu_sh7750.h>
+#elif defined (CONFIG_CPU_SH7780)
+#include <asm/cpu_sh7780.h>
+#else
+#error "Unknown SH4 variant"
+#endif
+#endif
diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h
new file mode 100644
index 0000000000..eb4f1affc2
--- /dev/null
+++ b/include/asm-sh/cpu_sh7750.h
@@ -0,0 +1,145 @@
+#ifndef _ASM_CPU_SH7750_H_
+#define _ASM_CPU_SH7750_H_
+
+#define PTEH 	0xFF000000 
+#define PTEL 	0xFF000004 
+#define TTB 	0xFF000008 
+#define TEA 	0xFF00000C 
+#define MMUCR 	0xFF000010 
+#define BASRA 	0xFF000014 
+#define BASRB	0xFF000018 
+#define CCR	0xFF00001C
+#define TRA 	0xFF000020
+#define EXPEVT 	0xFF000024
+#define INTEVT 	0xFF000028
+#define PTEA 	0xFF000034
+#define QACR0 	0xFF000038
+#define QACR1 	0xFF00003C
+#define BARA 	0xFF200000
+#define BAMRA 	0xFF200004
+#define BBRA 	0xFF200008
+#define BARB 	0xFF20000C
+#define BAMRB 	0xFF200010
+#define BBRB 	0xFF200014
+#define BDRB 	0xFF200018
+#define BDMRB 	0xFF20001C
+#define BRCR 	0xFF200020
+
+#define BCR1	0xFF800000
+#define BCR2	0xFF800004 
+#define BCR3 	0xFF800050 
+#define BCR4	0xFE0A00F0 
+#define WCR1 	0xFF800008 
+#define WCR2 	0xFF80000C 
+#define WCR3 	0xFF800010 
+#define MCR 	0xFF800014 
+#define PCR 	0xFF800018 
+#define RTCSR 	0xFF80001C 
+#define RTCNT 	0xFF800020 
+#define RTCOR 	0xFF800024 
+#define RFCR 	0xFF800028 
+#define PCTRA 	0xFF80002C 
+#define PDTRA 	0xFF800030 
+#define PCTRB 	0xFF800040 
+#define PDTRB 	0xFF800044 
+#define GPIOIC 	0xFF800048 
+#define SAR0 	0xFFA00000 
+#define DAR0 	0xFFA00004 
+#define DMATCR0 0xFFA00008 
+#define CHCR0	0xFFA0000C 
+#define SAR1 	0xFFA00010 
+#define DAR1 	0xFFA00014 
+#define DMATCR1 0xFFA00018 
+#define CHCR1 	0xFFA0001C 
+#define SAR2 	0xFFA00020 
+#define DAR2 	0xFFA00024 
+#define DMATCR2 0xFFA00028 
+#define CHCR2 	0xFFA0002C 
+#define SAR3 	0xFFA00030 
+#define DAR3 	0xFFA00034 
+#define DMATCR3 0xFFA00038 
+#define CHCR3 	0xFFA0003C 
+#define DMAOR 	0xFFA00040 
+#define SAR4	0xFFA00050 
+#define DAR4 	0xFFA00054 
+#define DMATCR4 0xFFA00058 
+
+#define FRQCR 	0xFFC00000 
+#define STBCR 	0xFFC00004 
+#define WTCNT 	0xFFC00008 
+#define WTCSR 	0xFFC0000C 
+#define STBCR2 	0xFFC00010 
+#define R64CNT	0xFFC80000 
+#define RSECCNT 0xFFC80004 
+#define RMINCNT 0xFFC80008 
+#define RHRCNT 	0xFFC8000C 
+#define RWKCNT 	0xFFC80010 
+#define RDAYCNT 0xFFC80014 
+#define RMONCNT 0xFFC80018 
+#define RYRCNT 	0xFFC8001C 
+#define RSECAR 	0xFFC80020 
+#define RMINAR 	0xFFC80024 
+#define RHRAR 	0xFFC80028 
+#define RWKAR 	0xFFC8002C 
+#define RDAYAR 	0xFFC80030 
+#define RMONAR 	0xFFC80034 
+#define RCR1 	0xFFC80038 
+#define RCR2 	0xFFC8003C 
+#define RCR3 	0xFFC80050 
+#define RYRAR 	0xFFC80054 
+#define ICR 	0xFFD00000 
+#define IPRA 	0xFFD00004 
+#define IPRB 	0xFFD00008 
+#define IPRC	0xFFD0000C 
+#define IPRD 	0xFFD00010 
+#define INTPRI 	0xFE080000 
+#define INTREQ	0xFE080020 
+#define INTMSK	0xFE080040 
+#define INTMSKCL	0xFE080060 
+#define CLKSTP		0xFE0A0000
+#define CLKSTPCLR	0xFE0A0008
+#define TSTR2 	0xFE100004 
+#define TCOR3 	0xFE100008 
+#define TCNT3 	0xFE10000C 
+#define TCR3 	0xFE100010 
+#define TCOR4 	0xFE100014 
+#define TCNT4 	0xFE100018 
+#define TCR4 	0xFE10001C 
+#define TOCR 	0xFFD80000 
+#define TSTR0 	0xFFD80004 
+#define TCOR0	0xFFD80008 
+#define TCNT0 	0xFFD8000C 
+#define TCR0 	0xFFD80010 
+#define TCOR1 	0xFFD80014 
+#define TCNT1 	0xFFD80018 
+#define TCR1 	0xFFD8001C 
+#define TCOR2 	0xFFD80020 
+#define TCNT2 	0xFFD80024 
+#define TCR2 	0xFFD80028 
+#define TCPR2 	0xFFD8002C
+#define SCSMR1 	0xFFE00000 
+#define SCBRR1 	0xFFE00004 
+#define SCSCR1 	0xFFE00008 
+#define SCTDR1 	0xFFE0000C 
+#define SCSSR1 	0xFFE00010 
+#define SCRDR1 	0xFFE00014 
+#define SCSCMR1 0xFFE00018 
+#define SCSPTR1 0xFFE0001C 
+#define SCF0_BASE	SCSMR1
+#define SCSMR2 	0xFFE80000
+#define SCBRR2 	0xFFE80004 
+#define SCSCR2 	0xFFE80008 
+#define SCFTDR2 0xFFE8000C 
+#define SCFSR2 	0xFFE80010 
+#define SCFRDR2	0xFFE80014 
+#define SCFCR2 	0xFFE80018 
+#define SCFDR2 	0xFFE8001C 
+#define SCSPTR2	0xFFE80020 
+#define SCLSR2 	0xFFE80024 
+#define SCIF1_BASE	SCSMR2
+#define SDIR 	0xFFF00000 
+#define SDDR 	0xFFF00008 
+#define SDINT 	0xFFF00014 
+
+#endif	/* _ASM_CPU_SH7750_H_ */
+
diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h
new file mode 100644
index 0000000000..0a44a34cef
--- /dev/null
+++ b/include/asm-sh/global_data.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_SH_GLOBALDATA_H_
+#define __ASM_SH_GLOBALDATA_H_
+
+typedef	struct global_data
+{
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	cpu_clk;	/* CPU clock in Hz! */
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid */
+	void		**jt;		/* Standalone app jump table */
+}gd_t;
+
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+
+#define DECLARE_GLOBAL_DATA_PTR	register gd_t *gd asm ("r13")
+
+#endif /* __ASM_SH_GLOBALDATA_H_ */
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
new file mode 100644
index 0000000000..70e60b170d
--- /dev/null
+++ b/include/asm-sh/io.h
@@ -0,0 +1,292 @@
+/*
+ *  linux/include/asm-sh/io.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_SH_IO_H
+#define __ASM_SH_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v,a)		__arch_putb(v,a)
+#define __raw_writew(v,a)		__arch_putw(v,a)
+#define __raw_writel(v,a)		__arch_putl(v,a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
+#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
+#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
+
+#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
+#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
+#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ */
+#if 0	/* XXX###XXX */
+#include <asm/arch/io.h>
+#endif	/* XXX###XXX */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The SH doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v,p)			__raw_writeb(v,__io(p))
+#define outw(v,p)			__raw_writew(cpu_to_le16(v),__io(p))
+#define outl(v,p)			__raw_writel(cpu_to_le32(v),__io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p,d,l)			__raw_writesb(__io(p),d,l)
+#define outsw(p,d,l)			__raw_writesw(__io(p),d,l)
+#define outsl(p,d,l)			__raw_writesl(__io(p),d,l)
+
+#define insb(p,d,l)			__raw_readsb(__io(p),d,l)
+#define insw(p,d,l)			__raw_readsw(__io(p),d,l)
+#define insl(p,d,l)			__raw_readsl(__io(p),d,l)
+#endif
+
+#define outb_p(val,port)		outb((val),(port))
+#define outw_p(val,port)		outw((val),(port))
+#define outl_p(val,port)		outl((val),(port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port,from,len)		outsb(port,from,len)
+#define outsw_p(port,from,len)		outsw(port,from,len)
+#define outsl_p(port,from,len)		outsl(port,from,len)
+#define insb_p(port,to,len)		insb(port,to,len)
+#define insw_p(port,to,len)		insw(port,to,len)
+#define insl_p(port,to,len)		insl(port,to,len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off,sz,nocache)				\
+ ({								\
+	unsigned long _off = (off), _size = (sz);		\
+	void *_ret = (void *)0;					\
+	if (iomem_valid_addr(_off, _size))			\
+		_ret = __ioremap(iomem_to_phys(_off),_size,0);	\
+	_ret;							\
+ })
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
+#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
+#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
+
+#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))
+
+#define eth_io_copy_and_sum(s,c,l,b) \
+				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"),0)
+#define readw(addr)			(__readwrite_bug("readw"),0)
+#define readl(addr)			(__readwrite_bug("readl"),0)
+#define writeb(v,addr)			__readwrite_bug("writeb")
+#define writew(v,addr)			__readwrite_bug("writew")
+#define writel(v,addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a,b,c,d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io,sig,len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val,addr)		__raw_writeb(val,__mem_isa(addr))
+#define isa_writew(val,addr)		__raw_writew(val,__mem_isa(addr))
+#define isa_writel(val,addr)		__raw_writel(val,__mem_isa(addr))
+#define isa_memset_io(a,b,c)		_memset_io(__mem_isa(a),(b),(c))
+#define isa_memcpy_fromio(a,b,c)	_memcpy_fromio((a),__mem_isa(b),(c))
+#define isa_memcpy_toio(a,b,c)		_memcpy_toio(__mem_isa((a)),(b),(c))
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+				eth_copy_and_sum((a),__mem_isa(b),(c),(d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+		    int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"),0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"),0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"),0)
+#define isa_writeb(val,addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val,addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val,addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a,b,c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a,b,c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a,b,c)		__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+				__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io,sig,len)	(0)
+
+static inline void sync(void)
+{
+}
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_SH_IO_H */
diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h
new file mode 100644
index 0000000000..4bb9f7e26f
--- /dev/null
+++ b/include/asm-sh/posix_types.h
@@ -0,0 +1,123 @@
+#ifndef __ASM_SH_POSIX_TYPES_H
+#define __ASM_SH_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short  __kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid_t;
+typedef unsigned short	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_timer_t;
+typedef int		__kernel_clockid_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+typedef unsigned short	__kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef	__FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef	__FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{ 
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef	__FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+	unsigned long *__tmp = __p->fds_bits;
+	int __i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+		case 16:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			__tmp[ 8] = 0; __tmp[ 9] = 0;
+			__tmp[10] = 0; __tmp[11] = 0;
+			__tmp[12] = 0; __tmp[13] = 0;
+			__tmp[14] = 0; __tmp[15] = 0;
+			return;
+
+		case 8:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			return;
+
+		case 4:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			return;
+		}
+	}
+	__i = __FDSET_LONGS;
+	while (__i) {
+		__i--;
+		*__tmp = 0;
+		__tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_SH_POSIX_TYPES_H */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
new file mode 100644
index 0000000000..bb9a35f643
--- /dev/null
+++ b/include/asm-sh/processor.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_SH_PROCESSOR_H_
+#define _ASM_SH_PROCESSOR_H_
+#if defined CONFIG_SH3
+# include <asm/cpu_sh3.h>
+#elif defined (CONFIG_SH4)
+# include <asm/cpu_sh4.h>
+#endif
+#endif
diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h
new file mode 100644
index 0000000000..14cc1aca63
--- /dev/null
+++ b/include/asm-sh/ptrace.h
@@ -0,0 +1,112 @@
+#ifndef __ASM_SH_PTRACE_H
+#define __ASM_SH_PTRACE_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka
+ * from linux kernel code.
+ */
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *	 0 - 15 are integer registers
+ *	17 - 22 are control/special registers
+ *	24 - 39 fp registers
+ *	40 - 47 xd registers
+ *	48 -    fpscr register
+ * -----------------------------
+ *
+ * We follows above, except:
+ *	16 --- program counter (PC)
+ *	22 --- syscall #
+ *	23 --- floating point communication register
+ */
+#define REG_REG0	 0
+#define REG_REG15	15
+
+#define REG_PC		16
+
+#define REG_PR		17
+#define REG_SR		18
+#define REG_GBR      	19
+#define REG_MACH	20
+#define REG_MACL	21
+
+#define REG_SYSCALL	22
+
+#define REG_FPREG0	23
+#define REG_FPREG15	38
+#define REG_XFREG0	39
+#define REG_XFREG15	54
+
+#define REG_FPSCR	55
+#define REG_FPUL	56
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD     0x00000001
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+	unsigned long regs[16];
+	unsigned long pc;
+	unsigned long pr;
+	unsigned long sr;
+	unsigned long gbr;
+	unsigned long mach;
+	unsigned long macl;
+	long tra;
+};
+
+/*
+ * This struct defines the way the DSP registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_dspregs {
+	unsigned long	a1;
+	unsigned long	a0g;
+	unsigned long	a1g;
+	unsigned long	m0;
+	unsigned long	m1;
+	unsigned long	a0;
+	unsigned long	x0;
+	unsigned long	x1;
+	unsigned long	y0;
+	unsigned long	y1;
+	unsigned long	dsr;
+	unsigned long	rs;
+	unsigned long	re;
+	unsigned long	mod;
+};
+
+#define	PTRACE_GETDSPREGS	55
+#define	PTRACE_SETDSPREGS	56
+
+#ifdef __KERNEL__
+#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
+#define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs(struct pt_regs *);
+
+#ifdef CONFIG_SH_DSP
+#define task_pt_regs(task) \
+	((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+		 - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
+#else
+#define task_pt_regs(task) \
+	((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+		 - sizeof(unsigned long)) - 1)
+#endif
+
+static inline unsigned long profile_pc(struct pt_regs *regs)
+{
+	unsigned long pc = instruction_pointer(regs);
+
+	if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
+		pc -= 0x20000000;
+	return pc;
+}
+#endif
+
+#endif /* __ASM_SH_PTRACE_H */
diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h
new file mode 100644
index 0000000000..a78ef818bc
--- /dev/null
+++ b/include/asm-sh/string.h
@@ -0,0 +1,132 @@
+#ifndef __ASM_SH_STRING_H
+#define __ASM_SH_STRING_H
+
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ * But consider these trivial functions to be public domain.
+ *
+ * from linux kernel code.
+ */
+
+#define __HAVE_ARCH_STRCPY
+static inline char *strcpy(char *__dest, const char *__src)
+{
+	register char *__xdest = __dest;
+	unsigned long __dummy;
+
+	__asm__ __volatile__("1:\n\t"
+			     "mov.b	@%1+, %2\n\t"
+			     "mov.b	%2, @%0\n\t"
+			     "cmp/eq	#0, %2\n\t"
+			     "bf/s	1b\n\t"
+			     " add	#1, %0\n\t"
+			     : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+			     : "0" (__dest), "1" (__src)
+			     : "memory", "t");
+
+	return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static inline char *strncpy(char *__dest, const char *__src, size_t __n)
+{
+	register char *__xdest = __dest;
+	unsigned long __dummy;
+
+	if (__n == 0)
+		return __xdest;
+
+	__asm__ __volatile__(
+		"1:\n"
+		"mov.b	@%1+, %2\n\t"
+		"mov.b	%2, @%0\n\t"
+		"cmp/eq	#0, %2\n\t"
+		"bt/s	2f\n\t"
+		" cmp/eq	%5,%1\n\t"
+		"bf/s	1b\n\t"
+		" add	#1, %0\n"
+		"2:"
+		: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+		: "0" (__dest), "1" (__src), "r" (__src+__n)
+		: "memory", "t");
+
+	return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static inline int strcmp(const char *__cs, const char *__ct)
+{
+	register int __res;
+	unsigned long __dummy;
+
+	__asm__ __volatile__(
+		"mov.b	@%1+, %3\n"
+		"1:\n\t"
+		"mov.b	@%0+, %2\n\t"
+		"cmp/eq #0, %3\n\t"
+		"bt	2f\n\t"
+		"cmp/eq %2, %3\n\t"
+		"bt/s	1b\n\t"
+		" mov.b	@%1+, %3\n\t"
+		"add	#-2, %1\n\t"
+		"mov.b	@%1, %3\n\t"
+		"sub	%3, %2\n"
+		"2:"
+		: "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+		: "0" (__cs), "1" (__ct)
+		: "t");
+
+	return __res;
+}
+
+#define __HAVE_ARCH_STRNCMP
+static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
+{
+	register int __res;
+	unsigned long __dummy;
+
+	if (__n == 0)
+		return 0;
+
+	__asm__ __volatile__(
+		"mov.b	@%1+, %3\n"
+		"1:\n\t"
+		"mov.b	@%0+, %2\n\t"
+		"cmp/eq %6, %0\n\t"
+		"bt/s	2f\n\t"
+		" cmp/eq #0, %3\n\t"
+		"bt/s	3f\n\t"
+		" cmp/eq %3, %2\n\t"
+		"bt/s	1b\n\t"
+		" mov.b	@%1+, %3\n\t"
+		"add	#-2, %1\n\t"
+		"mov.b	@%1, %3\n"
+		"2:\n\t"
+		"sub	%3, %2\n"
+		"3:"
+		:"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+		: "0" (__cs), "1" (__ct), "r" (__cs+__n)
+		: "t");
+
+	return __res;
+}
+
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *__s, int __c, size_t __n);
+
+#undef __HAVE_ARCH_STRLEN
+extern size_t strlen(const char *);
+
+/* arch/sh/lib/strcasecmp.c */
+extern int strcasecmp(const char *, const char *);
+
+#endif /* __ASM_SH_STRING_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
new file mode 100644
index 0000000000..b353bc5c3b
--- /dev/null
+++ b/include/asm-sh/system.h
@@ -0,0 +1,275 @@
+#ifndef __ASM_SH_SYSTEM_H
+#define __ASM_SH_SYSTEM_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
+ * Copyright (C) 2002 Paul Mundt
+ *
+ * from linux kernel code.
+ */
+
+#include <linux/irqflags.h>
+#include <asm/types.h>
+
+/*
+ *	switch_to() should switch tasks to task nr n, first
+ */
+
+#define switch_to(prev, next, last) do {				\
+ struct task_struct *__last;						\
+ register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp;	\
+ register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc;	\
+ register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev;	\
+ register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next;	\
+ register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp;	\
+ register unsigned long __ts7 __asm__ ("r7") = next->thread.pc;		\
+ __asm__ __volatile__ (".balign 4\n\t" 					\
+		       "stc.l	gbr, @-r15\n\t" 			\
+		       "sts.l	pr, @-r15\n\t" 				\
+		       "mov.l	r8, @-r15\n\t" 				\
+		       "mov.l	r9, @-r15\n\t" 				\
+		       "mov.l	r10, @-r15\n\t" 			\
+		       "mov.l	r11, @-r15\n\t" 			\
+		       "mov.l	r12, @-r15\n\t" 			\
+		       "mov.l	r13, @-r15\n\t" 			\
+		       "mov.l	r14, @-r15\n\t" 			\
+		       "mov.l	r15, @r1	! save SP\n\t"		\
+		       "mov.l	@r6, r15	! change to new stack\n\t" \
+		       "mova	1f, %0\n\t" 				\
+		       "mov.l	%0, @r2		! save PC\n\t" 		\
+		       "mov.l	2f, %0\n\t" 				\
+		       "jmp	@%0		! call __switch_to\n\t" \
+		       " lds	r7, pr		!  with return to new PC\n\t" \
+		       ".balign	4\n"					\
+		       "2:\n\t"						\
+		       ".long	__switch_to\n"				\
+		       "1:\n\t"						\
+		       "mov.l	@r15+, r14\n\t"				\
+		       "mov.l	@r15+, r13\n\t"				\
+		       "mov.l	@r15+, r12\n\t"				\
+		       "mov.l	@r15+, r11\n\t"				\
+		       "mov.l	@r15+, r10\n\t"				\
+		       "mov.l	@r15+, r9\n\t"				\
+		       "mov.l	@r15+, r8\n\t"				\
+		       "lds.l	@r15+, pr\n\t"				\
+		       "ldc.l	@r15+, gbr\n\t"				\
+		       : "=z" (__last)					\
+		       : "r" (__ts1), "r" (__ts2), "r" (__ts4), 	\
+			 "r" (__ts5), "r" (__ts6), "r" (__ts7) 		\
+		       : "r3", "t");					\
+	last = __last;							\
+} while (0)
+
+/*
+ * On SMP systems, when the scheduler does migration-cost autodetection,
+ * it needs a way to flush as much of the CPU's caches as possible.
+ *
+ * TODO: fill this in!
+ */
+static inline void sched_cacheflush(void)
+{
+}
+
+#ifdef CONFIG_CPU_SH4A
+#define __icbi()			\
+{					\
+	unsigned long __addr;		\
+	__addr = 0xa8000000;		\
+	__asm__ __volatile__(		\
+		"icbi   %0\n\t"		\
+		: /* no output */	\
+		: "m" (__m(__addr)));	\
+}
+#endif
+
+static inline unsigned long tas(volatile int *m)
+{
+	unsigned long retval;
+
+	__asm__ __volatile__ ("tas.b	@%1\n\t"
+			      "movt	%0"
+			      : "=r" (retval): "r" (m): "t", "memory");
+	return retval;
+}
+
+/*
+ * A brief note on ctrl_barrier(), the control register write barrier.
+ *
+ * Legacy SH cores typically require a sequence of 8 nops after
+ * modification of a control register in order for the changes to take
+ * effect. On newer cores (like the sh4a and sh5) this is accomplished
+ * with icbi.
+ *
+ * Also note that on sh4a in the icbi case we can forego a synco for the
+ * write barrier, as it's not necessary for control registers.
+ *
+ * Historically we have only done this type of barrier for the MMUCR, but
+ * it's also necessary for the CCR, so we make it generic here instead.
+ */
+#ifdef CONFIG_CPU_SH4A
+#define mb()		__asm__ __volatile__ ("synco": : :"memory")
+#define rmb()		mb()
+#define wmb()		__asm__ __volatile__ ("synco": : :"memory")
+#define ctrl_barrier()	__icbi()
+#define read_barrier_depends()	do { } while(0)
+#else
+#define mb()		__asm__ __volatile__ ("": : :"memory")
+#define rmb()		mb()
+#define wmb()		__asm__ __volatile__ ("": : :"memory")
+#define ctrl_barrier()	__asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
+#define read_barrier_depends()	do { } while(0)
+#endif
+
+#ifdef CONFIG_SMP
+#define smp_mb()	mb()
+#define smp_rmb()	rmb()
+#define smp_wmb()	wmb()
+#define smp_read_barrier_depends()	read_barrier_depends()
+#else
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#define smp_read_barrier_depends()	do { } while(0)
+#endif
+
+#define set_mb(var, value) do { xchg(&var, value); } while (0)
+
+/*
+ * Jump to P2 area.
+ * When handling TLB or caches, we need to do it from P2 area.
+ */
+#define jump_to_P2()			\
+do {					\
+	unsigned long __dummy;		\
+	__asm__ __volatile__(		\
+		"mov.l	1f, %0\n\t"	\
+		"or	%1, %0\n\t"	\
+		"jmp	@%0\n\t"	\
+		" nop\n\t" 		\
+		".balign 4\n"		\
+		"1:	.long 2f\n"	\
+		"2:"			\
+		: "=&r" (__dummy)	\
+		: "r" (0x20000000));	\
+} while (0)
+
+/*
+ * Back to P1 area.
+ */
+#define back_to_P1()					\
+do {							\
+	unsigned long __dummy;				\
+	ctrl_barrier();					\
+	__asm__ __volatile__(				\
+		"mov.l	1f, %0\n\t"			\
+		"jmp	@%0\n\t"			\
+		" nop\n\t"				\
+		".balign 4\n"				\
+		"1:	.long 2f\n"			\
+		"2:"					\
+		: "=&r" (__dummy));			\
+} while (0)
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+	unsigned long flags, retval;
+
+	local_irq_save(flags);
+	retval = *m;
+	*m = val;
+	local_irq_restore(flags);
+	return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+	unsigned long flags, retval;
+
+	local_irq_save(flags);
+	retval = *m;
+	*m = val & 0xff;
+	local_irq_restore(flags);
+	return retval;
+}
+
+extern void __xchg_called_with_bad_pointer(void);
+
+#define __xchg(ptr, x, size)				\
+({							\
+	unsigned long __xchg__res;			\
+	volatile void *__xchg_ptr = (ptr);		\
+	switch (size) {					\
+	case 4:						\
+		__xchg__res = xchg_u32(__xchg_ptr, x);	\
+		break;					\
+	case 1:						\
+		__xchg__res = xchg_u8(__xchg_ptr, x);	\
+		break;					\
+	default:					\
+		__xchg_called_with_bad_pointer();	\
+		__xchg__res = x;			\
+		break;					\
+	}						\
+							\
+	__xchg__res;					\
+})
+
+#define xchg(ptr,x)	\
+	((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
+
+static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
+	unsigned long new)
+{
+	__u32 retval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	retval = *m;
+	if (retval == old)
+		*m = new;
+	local_irq_restore(flags);       /* implies memory barrier  */
+	return retval;
+}
+
+/* This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg(). */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
+		unsigned long new, int size)
+{
+	switch (size) {
+	case 4:
+		return __cmpxchg_u32(ptr, old, new);
+	}
+	__cmpxchg_called_with_bad_pointer();
+	return old;
+}
+
+#define cmpxchg(ptr,o,n)						 \
+  ({									 \
+     __typeof__(*(ptr)) _o_ = (o);					 \
+     __typeof__(*(ptr)) _n_ = (n);					 \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
+				    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+extern void *set_exception_table_vec(unsigned int vec, void *handler);
+
+static inline void *set_exception_table_evt(unsigned int evt, void *handler)
+{
+	return set_exception_table_vec(evt >> 5, handler);
+}
+
+/* XXX
+ * disable hlt during certain critical i/o operations
+ */
+#define HAVE_DISABLE_HLT
+void disable_hlt(void);
+void enable_hlt(void);
+
+#define arch_align_stack(x) (x)
+
+#endif
diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h
new file mode 100644
index 0000000000..fd00dbb82f
--- /dev/null
+++ b/include/asm-sh/types.h
@@ -0,0 +1,59 @@
+#ifndef __ASM_SH_TYPES_H
+#define __ASM_SH_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+
+typedef __signed__ char s8;
+typedef unsigned char u8;
+
+typedef __signed__ short s16;
+typedef unsigned short u16;
+
+typedef __signed__ int s32;
+typedef unsigned int u32;
+
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_TYPES_H */
diff --git a/include/asm-sh/u-boot.h b/include/asm-sh/u-boot.h
new file mode 100644
index 0000000000..c74e97cdfb
--- /dev/null
+++ b/include/asm-sh/u-boot.h
@@ -0,0 +1,44 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_SH_U_BOOT_H_
+#define __ASM_SH_U_BOOT_H_
+
+
+typedef struct bd_info {
+	unsigned long   bi_memstart;    /* start of DRAM memory */
+	unsigned long   bi_memsize;     /* size  of DRAM memory in bytes */
+	unsigned long   bi_flashstart;  /* start of FLASH memory */
+	unsigned long   bi_flashsize;   /* size  of FLASH memory */
+	unsigned long   bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long   bi_sramstart;   /* start of SRAM memory */
+	unsigned long   bi_sramsize;    /* size  of SRAM memory */
+	unsigned long   bi_ip_addr;     /* IP Address */
+	unsigned char   bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long   bi_baudrate;    /* Console Baudrate */
+	unsigned long	bi_boot_params; /* where this board expects params */
+} bd_t;
+
+#endif
+