Merge branch 'master' of git://git.denx.de/u-boot-socfpga

19 files changed, 1695 insertions, 481 deletions

diff --git a/drivers/Makefile b/drivers/Makefile
index b51bdeedbe..44a08da602 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
 obj-$(CONFIG_$(SPL_TPL_)DM) += core/
 obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 629039e7a8..1e452ad6d9 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -31,4 +31,12 @@ config V5L2_CACHE
 	  It will configure tag and data ram timing control from the
 	  device tree and enable L2 cache.
 
+config NCORE_CACHE
+	bool "Arteris Ncore cache coherent unit driver"
+	select CACHE
+	help
+	  This driver is for the Arteris Ncore cache coherent unit (CCU)
+	  controller. The driver initializes cache directories and coherent
+	  agent interfaces.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 4a6458c602..fed50be3f9 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -1,5 +1,6 @@
 
-obj-$(CONFIG_CACHE) += cache-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-ncore.c b/drivers/cache/cache-ncore.c
new file mode 100644
index 0000000000..e3aca36071
--- /dev/null
+++ b/drivers/cache/cache-ncore.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+#include <dm.h>
+#include <wait_bit.h>
+
+#include <asm/io.h>
+
+/* Directory */
+#define DIRUSFER		0x80010
+#define DIRUCASER0		0x80040
+#define DIRUSFMCR		0x80080
+#define DIRUSFMAR		0x80084
+
+#define DIRUSFMCR_SFID_SHIFT	16
+
+/* Coherent cache agent interface */
+#define CAIUIDR			0x00ffc
+
+#define CAIUIDR_CA_GET(v)	(((v) & 0x00008000) >> 15)
+#define CAIUIDR_TYPE_GET(v)	(((v) & 0x000f0000) >> 16)
+#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT	0
+#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT	1
+
+/* Coherent subsystem */
+#define CSADSER0		0xff040
+#define CSUIDR			0xffff8
+#define CSIDR			0xffffc
+
+#define CSUIDR_NUMCAIUS_GET(v)	(((v) & 0x0000007f) >> 0)
+#define CSUIDR_NUMDIRUS_GET(v)	(((v) & 0x003f0000) >> 16)
+#define CSUIDR_NUMCMIUS_GET(v)	(((v) & 0x3f000000) >> 24)
+
+#define CSIDR_NUMSFS_GET(v)	(((v) & 0x007c0000) >> 18)
+
+#define DIR_REG_SZ		0x1000
+#define CAIU_REG_SZ		0x1000
+
+#define CCU_DIR_REG_ADDR(base, reg, dir)	\
+		((base) + (reg) + ((dir) * DIR_REG_SZ))
+
+/* OCRAM firewall register */
+#define OCRAM_FW_01			0x100204
+#define OCRAM_SECURE_REGIONS		4
+
+#define OCRAM_PRIVILEGED_MASK		BIT(29)
+#define OCRAM_SECURE_MASK		BIT(30)
+
+static void ncore_ccu_init_dirs(void __iomem *base)
+{
+	ulong i, f;
+	int ret;
+	u32 num_of_dirs;
+	u32 num_of_snoop_filters;
+	u32 reg;
+
+	num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
+	num_of_snoop_filters =
+		CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
+
+	/* Initialize each snoop filter in each directory */
+	for (f = 0; f < num_of_snoop_filters; f++) {
+		reg = f << DIRUSFMCR_SFID_SHIFT;
+		for (i = 0; i < num_of_dirs; i++) {
+			/* Initialize all entries */
+			writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
+
+			/* Poll snoop filter maintenance operation active
+			 * bit become 0.
+			 */
+			ret = wait_for_bit_le32((const void *)
+						CCU_DIR_REG_ADDR(base,
+								 DIRUSFMAR, i),
+						BIT(0), false, 1000, false);
+			if (ret) {
+				puts("CCU: Directory initialization failed!\n");
+				hang();
+			}
+
+			/* Enable snoop filter, a bit per snoop filter */
+			setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
+				     BIT(f));
+		}
+	}
+}
+
+static void ncore_ccu_init_coh_agent(void __iomem *base)
+{
+	u32 num_of_coh_agent_intf;
+	u32 num_of_dirs;
+	u32 reg;
+	u32 type;
+	u32 i, dir;
+
+	num_of_coh_agent_intf =
+		CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
+	num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
+
+	for (i = 0; i < num_of_coh_agent_intf; i++) {
+		reg = readl(base + CAIUIDR + (i * CAIU_REG_SZ));
+		if (CAIUIDR_CA_GET(reg)) {
+			/* Caching agent bit is enabled, enable caching agent
+			 * snoop in each directory
+			 */
+			for (dir = 0; dir < num_of_dirs; dir++) {
+				setbits_le32((ulong)
+					     CCU_DIR_REG_ADDR(base, DIRUCASER0,
+							      dir),
+					     BIT(i));
+			}
+		}
+
+		type = CAIUIDR_TYPE_GET(reg);
+		if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||
+		    type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {
+			/* DVM support is enabled, enable ACE DVM snoop*/
+			setbits_le32((ulong)(base + CSADSER0),
+				     BIT(i));
+		}
+	}
+}
+
+static void ocram_bypass_firewall(void __iomem *base)
+{
+	int i;
+
+	for (i = 0; i < OCRAM_SECURE_REGIONS; i++) {
+		clrbits_le32(base + OCRAM_FW_01 + (i * sizeof(u32)),
+			     OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
+	}
+}
+
+static int ncore_ccu_probe(struct udevice *dev)
+{
+	void __iomem *base;
+	fdt_addr_t addr;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	base = (void __iomem *)addr;
+
+	ncore_ccu_init_dirs(base);
+	ncore_ccu_init_coh_agent(base);
+	ocram_bypass_firewall(base);
+
+	return 0;
+}
+
+static const struct udevice_id ncore_ccu_ids[] = {
+	{ .compatible = "arteris,ncore-ccu" },
+	{}
+};
+
+U_BOOT_DRIVER(ncore_ccu) = {
+	.name   = "ncore_ccu",
+	.id     = UCLASS_CACHE,
+	.of_match = ncore_ccu_ids,
+	.probe	= ncore_ccu_probe,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index a3ae8b24b0..96215ad5c4 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -3,4 +3,5 @@
 # Copyright (C) 2018 Marek Vasut <marex@denx.de>
 #
 
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
new file mode 100644
index 0000000000..5fedec549d
--- /dev/null
+++ b/drivers/clk/altera/clk-agilex.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+#include <dt-bindings/clock/agilex-clock.h>
+
+#include <asm/arch/clock_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_platdata {
+	void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
+{
+	CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+	cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
+{
+	CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+	cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
+{
+	CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+	cm_wait_for_fsm();
+}
+
+#define MEMBUS_MAINPLL				0
+#define MEMBUS_PERPLL				1
+#define MEMBUS_TIMEOUT				1000
+#define MEMBUS_ADDR_CLKSLICE			0x27
+#define MEMBUS_CLKSLICE_SYNC_MODE_EN		0x80
+
+static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
+			       int timeout)
+{
+	int cnt = 0;
+	u32 req_status;
+
+	if (pll == MEMBUS_MAINPLL)
+		req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+	else
+		req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+
+	while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
+		if (pll == MEMBUS_MAINPLL)
+			req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+		else
+			req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+		cnt++;
+	}
+
+	if (cnt >= timeout)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
+			    u32 addr_offset, u32 wdat, int timeout)
+{
+	u32 addr;
+	u32 val;
+
+	addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
+
+	val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
+	       (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
+
+	if (pll == MEMBUS_MAINPLL)
+		CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
+	else
+		CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
+
+	debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
+
+	return membus_wait_for_req(plat, pll, timeout);
+}
+
+static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
+			   u32 addr_offset, u32 *rdata, int timeout)
+{
+	u32 addr;
+	u32 val;
+
+	addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
+
+	val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr);
+
+	if (pll == MEMBUS_MAINPLL)
+		CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
+	else
+		CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
+
+	*rdata = 0;
+
+	if (membus_wait_for_req(plat, pll, timeout))
+		return -ETIMEDOUT;
+
+	if (pll == MEMBUS_MAINPLL)
+		*rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT);
+	else
+		*rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT);
+
+	debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr);
+
+	return 0;
+}
+
+static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
+{
+	u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
+
+	mdiv = pllm & CLKMGR_PLLM_MDIV_MASK;
+	arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
+		      CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
+	drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >>
+		      CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET;
+	refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >>
+		     CLKMGR_PLLGLOB_REFCLKDIV_OFFSET;
+	mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv));
+	if (!mscnt)
+		mscnt = 1;
+	hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) -
+		CLKMGR_VCOCALIB_HSCNT_CONST;
+	vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+		   ((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) &
+		     CLKMGR_VCOCALIB_MSCNT_MASK);
+
+	/* Dump all the pll calibration settings for debug purposes */
+	debug("mdiv          : %d\n", mdiv);
+	debug("arefclkdiv    : %d\n", arefclkdiv);
+	debug("drefclkdiv    : %d\n", drefclkdiv);
+	debug("refclkdiv     : %d\n", refclkdiv);
+	debug("mscnt         : %d\n", mscnt);
+	debug("hscnt         : %d\n", hscnt);
+	debug("vcocalib      : 0x%08x\n", vcocalib);
+
+	return vcocalib;
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+			   const struct cm_config * const cfg)
+{
+	struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+	u32 vcocalib;
+	u32 rdata;
+
+	if (!cfg)
+		return;
+
+	/* Put both PLLs in bypass */
+	clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+	clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+	/* Put both PLLs in Reset and Power Down */
+	CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
+		       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+	CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB,
+		       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+	/* setup main PLL dividers where calculate the vcocalib value */
+	vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
+		      CLKMGR_MAINPLL_PLLGLOB);
+	CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK);
+	CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3);
+	CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM);
+	CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+	CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+	CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+	/* setup peripheral PLL dividers where calculate the vcocalib value */
+	vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
+		      CLKMGR_PERPLL_PLLGLOB);
+	CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK);
+	CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3);
+	CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM);
+	CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+	CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+	/* Take both PLL out of reset and power up */
+	CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
+		       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+	CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
+		       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+	/* Membus programming to set mainpll and perripll to
+	 * source synchronous mode
+	 */
+	membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
+			MEMBUS_TIMEOUT);
+	membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE,
+			 (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
+			 MEMBUS_TIMEOUT);
+	membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
+			MEMBUS_TIMEOUT);
+	membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE,
+			 (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
+			 MEMBUS_TIMEOUT);
+
+	cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+	/* Configure ping pong counters in altera group */
+	CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+	CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+	CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+	CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
+	CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
+	CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
+	CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
+	CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
+
+	CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
+	CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
+
+	CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
+			CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+			CLKMGR_MAINPLL_PLLGLOB);
+	CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
+			CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+			CLKMGR_PERPLL_PLLGLOB);
+
+	/* Take all PLLs out of bypass */
+	clk_write_bypass_mainpll(plat, 0);
+	clk_write_bypass_perpll(plat, 0);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
+		       CLKMGR_INTER_PERPLLLOST_MASK |
+		       CLKMGR_INTER_MAINPLLLOST_MASK);
+
+	/* Take all ping pong counters out of reset */
+	CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
+		       CLKMGR_ALT_EXTCNTRST_ALLCNTRST);
+
+	/* Out of boot mode */
+	clk_write_ctrl(plat,
+		       CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
+}
+
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
+			      u32 pllglob_reg, u32 pllm_reg)
+{
+	 u64 fref, arefdiv, mdiv, reg, vco;
+
+	reg = CM_REG_READL(plat, pllglob_reg);
+
+	fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
+		CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
+
+	switch (fref) {
+	case CLKMGR_VCO_PSRC_EOSC1:
+		fref = cm_get_osc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_INTOSC:
+		fref = cm_get_intosc_clk_hz();
+		break;
+	case CLKMGR_VCO_PSRC_F2S:
+		fref = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
+		   CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
+
+	mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK;
+
+	vco = fref / arefdiv;
+	vco = vco * mdiv;
+
+	return vco;
+}
+
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
+				 CLKMGR_MAINPLL_PLLM);
+}
+
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
+				 CLKMGR_PERPLL_PLLM);
+}
+
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
+{
+	u32 clksrc = CM_REG_READL(plat, reg);
+
+	return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
+}
+
+static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
+			     u32 main_reg, u32 per_reg)
+{
+	u64 clock;
+	u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
+
+	switch (clklsrc) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = clk_get_main_vco_clk_hz(plat);
+		clock /= (CM_REG_READL(plat, main_reg) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = clk_get_per_vco_clk_hz(plat);
+		clock /= (CM_REG_READL(plat, per_reg) &
+			  CLKMGR_CLKCNT_MSK);
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	default:
+		return 0;
+	}
+
+	return clock;
+}
+
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
+				      CLKMGR_MAINPLL_PLLC0,
+				      CLKMGR_PERPLL_PLLC0);
+
+	clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
+		 CLKMGR_CLKCNT_MSK);
+
+	return clock;
+}
+
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
+				      CLKMGR_MAINPLL_PLLC1,
+				      CLKMGR_PERPLL_PLLC1);
+}
+
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_l3_main_clk_hz(plat);
+
+	clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+	      CLKMGR_NOCDIV_L4MAIN_OFFSET) &
+	      CLKMGR_NOCDIV_DIVIDER_MASK);
+
+	return clock;
+}
+
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
+				      CLKMGR_MAINPLL_PLLC3,
+				      CLKMGR_PERPLL_PLLC3);
+
+	clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
+		 CLKMGR_CLKCNT_MSK);
+
+	return clock / 4;
+}
+
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_l3_main_clk_hz(plat);
+
+	clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+		      CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
+		      CLKMGR_NOCDIV_DIVIDER_MASK);
+
+	return clock;
+}
+
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	u64 clock = clk_get_l3_main_clk_hz(plat);
+
+	clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+		      CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
+		      CLKMGR_NOCDIV_DIVIDER_MASK);
+
+	return clock;
+}
+
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
+{
+	if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
+		return clk_get_l3_main_clk_hz(plat) / 2;
+
+	return clk_get_l3_main_clk_hz(plat) / 4;
+}
+
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
+{
+	bool emacsel_a;
+	u32 ctl;
+	u32 ctr_reg;
+	u32 clock;
+	u32 div;
+	u32 reg;
+
+	/* Get EMAC clock source */
+	ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
+	if (emac_id == AGILEX_EMAC0_CLK)
+		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
+	else if (emac_id == AGILEX_EMAC1_CLK)
+		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
+	else if (emac_id == AGILEX_EMAC2_CLK)
+		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
+	else
+		return 0;
+
+	if (ctl) {
+		/* EMAC B source */
+		emacsel_a = false;
+		ctr_reg = CLKMGR_ALTR_EMACBCTR;
+	} else {
+		/* EMAC A source */
+		emacsel_a = true;
+		ctr_reg = CLKMGR_ALTR_EMACACTR;
+	}
+
+	reg = CM_REG_READL(plat, ctr_reg);
+	clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
+		 >> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
+	div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
+		>> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
+
+	switch (clock) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = clk_get_main_vco_clk_hz(plat);
+		if (emacsel_a) {
+			clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) &
+				  CLKMGR_CLKCNT_MSK);
+		} else {
+			clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) &
+				  CLKMGR_CLKCNT_MSK);
+		}
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = clk_get_per_vco_clk_hz(plat);
+		if (emacsel_a) {
+			clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) &
+				  CLKMGR_CLKCNT_MSK);
+		} else {
+			clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) &
+				  CLKMGR_CLKCNT_MSK);
+		}
+		break;
+
+	case CLKMGR_CLKSRC_OSC1:
+		clock = cm_get_osc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_INTOSC:
+		clock = cm_get_intosc_clk_hz();
+		break;
+
+	case CLKMGR_CLKSRC_FPGA:
+		clock = cm_get_fpga_clk_hz();
+		break;
+	}
+
+	clock /= 1 + div;
+
+	return clock;
+}
+
+static ulong socfpga_clk_get_rate(struct clk *clk)
+{
+	struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);
+
+	switch (clk->id) {
+	case AGILEX_MPU_CLK:
+		return clk_get_mpu_clk_hz(plat);
+	case AGILEX_L4_MAIN_CLK:
+		return clk_get_l4_main_clk_hz(plat);
+	case AGILEX_L4_SYS_FREE_CLK:
+		return clk_get_l4_sys_free_clk_hz(plat);
+	case AGILEX_L4_MP_CLK:
+		return clk_get_l4_mp_clk_hz(plat);
+	case AGILEX_L4_SP_CLK:
+		return clk_get_l4_sp_clk_hz(plat);
+	case AGILEX_SDMMC_CLK:
+		return clk_get_sdmmc_clk_hz(plat);
+	case AGILEX_EMAC0_CLK:
+	case AGILEX_EMAC1_CLK:
+	case AGILEX_EMAC2_CLK:
+		return clk_get_emac_clk_hz(plat, clk->id);
+	case AGILEX_USB_CLK:
+		return clk_get_l4_mp_clk_hz(plat);
+	default:
+		return -ENXIO;
+	}
+}
+
+static int socfpga_clk_probe(struct udevice *dev)
+{
+	const struct cm_config *cm_default_cfg = cm_get_default_config();
+
+	clk_basic_init(dev, cm_default_cfg);
+
+	return 0;
+}
+
+static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
+{
+	struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
+	fdt_addr_t addr;
+
+	addr = devfdt_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->regs = (void __iomem *)addr;
+
+	return 0;
+}
+
+static struct clk_ops socfpga_clk_ops = {
+	.get_rate	= socfpga_clk_get_rate,
+};
+
+static const struct udevice_id socfpga_clk_match[] = {
+	{ .compatible = "intel,agilex-clkmgr" },
+	{}
+};
+
+U_BOOT_DRIVER(socfpga_agilex_clk) = {
+	.name		= "clk-agilex",
+	.id		= UCLASS_CLK,
+	.of_match	= socfpga_clk_match,
+	.ops		= &socfpga_clk_ops,
+	.probe		= socfpga_clk_probe,
+	.ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct socfpga_clk_platdata),
+};
diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h
new file mode 100644
index 0000000000..d93328ef29
--- /dev/null
+++ b/drivers/clk/altera/clk-agilex.h
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef	_CLK_AGILEX_
+#define	_CLK_AGILEX_
+
+#define CM_REG_READL(plat, reg)				\
+	readl((plat)->regs + (reg))
+
+#define CM_REG_WRITEL(plat, data, reg)			\
+	writel(data, (plat)->regs + (reg))
+
+#define CM_REG_CLRBITS(plat, reg, clear)		\
+	clrbits_le32((plat)->regs + (reg), (clear))
+
+#define CM_REG_SETBITS(plat, reg, set)			\
+	setbits_le32((plat)->regs + (reg), (set))
+
+struct cm_config {
+	/* main group */
+	u32 main_pll_mpuclk;
+	u32 main_pll_nocclk;
+	u32 main_pll_nocdiv;
+	u32 main_pll_pllglob;
+	u32 main_pll_fdbck;
+	u32 main_pll_pllc0;
+	u32 main_pll_pllc1;
+	u32 main_pll_pllc2;
+	u32 main_pll_pllc3;
+	u32 main_pll_pllm;
+
+	/* peripheral group */
+	u32 per_pll_emacctl;
+	u32 per_pll_gpiodiv;
+	u32 per_pll_pllglob;
+	u32 per_pll_fdbck;
+	u32 per_pll_pllc0;
+	u32 per_pll_pllc1;
+	u32 per_pll_pllc2;
+	u32 per_pll_pllc3;
+	u32 per_pll_pllm;
+
+	/* altera group */
+	u32 alt_emacactr;
+	u32 alt_emacbctr;
+	u32 alt_emacptpctr;
+	u32 alt_gpiodbctr;
+	u32 alt_sdmmcctr;
+	u32 alt_s2fuser0ctr;
+	u32 alt_s2fuser1ctr;
+	u32 alt_psirefctr;
+
+	/* incoming clock */
+	u32 hps_osc_clk_hz;
+	u32 fpga_clk_hz;
+	u32 spare[3];
+};
+
+/* Clock Manager registers */
+#define CLKMGR_CTRL				0
+#define CLKMGR_STAT				4
+#define CLKMGR_TESTIOCTRL			8
+#define CLKMGR_INTRGEN				0x0c
+#define CLKMGR_INTRMSK				0x10
+#define CLKMGR_INTRCLR				0x14
+#define CLKMGR_INTRSTS				0x18
+#define CLKMGR_INTRSTK				0x1c
+#define CLKMGR_INTRRAW				0x20
+
+/* Clock Manager Main PPL group registers */
+#define CLKMGR_MAINPLL_EN			0x24
+#define CLKMGR_MAINPLL_ENS			0x28
+#define CLKMGR_MAINPLL_ENR			0x2c
+#define CLKMGR_MAINPLL_BYPASS			0x30
+#define CLKMGR_MAINPLL_BYPASSS			0x34
+#define CLKMGR_MAINPLL_BYPASSR			0x38
+#define CLKMGR_MAINPLL_MPUCLK			0x3c
+#define CLKMGR_MAINPLL_NOCCLK			0x40
+#define CLKMGR_MAINPLL_NOCDIV			0x44
+#define CLKMGR_MAINPLL_PLLGLOB			0x48
+#define CLKMGR_MAINPLL_FDBCK			0x4c
+#define CLKMGR_MAINPLL_MEM			0x50
+#define CLKMGR_MAINPLL_MEMSTAT			0x54
+#define CLKMGR_MAINPLL_PLLC0			0x58
+#define CLKMGR_MAINPLL_PLLC1			0x5c
+#define CLKMGR_MAINPLL_VCOCALIB			0x60
+#define CLKMGR_MAINPLL_PLLC2			0x64
+#define CLKMGR_MAINPLL_PLLC3			0x68
+#define CLKMGR_MAINPLL_PLLM			0x6c
+#define CLKMGR_MAINPLL_FHOP			0x70
+#define CLKMGR_MAINPLL_SSC			0x74
+#define CLKMGR_MAINPLL_LOSTLOCK			0x78
+
+/* Clock Manager Peripheral PPL group registers */
+#define CLKMGR_PERPLL_EN			0x7c
+#define CLKMGR_PERPLL_ENS			0x80
+#define CLKMGR_PERPLL_ENR			0x84
+#define CLKMGR_PERPLL_BYPASS			0x88
+#define CLKMGR_PERPLL_BYPASSS			0x8c
+#define CLKMGR_PERPLL_BYPASSR			0x90
+#define CLKMGR_PERPLL_EMACCTL			0x94
+#define CLKMGR_PERPLL_GPIODIV			0x98
+#define CLKMGR_PERPLL_PLLGLOB			0x9c
+#define CLKMGR_PERPLL_FDBCK			0xa0
+#define CLKMGR_PERPLL_MEM			0xa4
+#define CLKMGR_PERPLL_MEMSTAT			0xa8
+#define CLKMGR_PERPLL_PLLC0			0xac
+#define CLKMGR_PERPLL_PLLC1			0xb0
+#define CLKMGR_PERPLL_VCOCALIB			0xb4
+#define CLKMGR_PERPLL_PLLC2			0xb8
+#define CLKMGR_PERPLL_PLLC3			0xbc
+#define CLKMGR_PERPLL_PLLM			0xc0
+#define CLKMGR_PERPLL_FHOP			0xc4
+#define CLKMGR_PERPLL_SSC			0xc8
+#define CLKMGR_PERPLL_LOSTLOCK			0xcc
+
+/* Clock Manager Altera group registers */
+#define CLKMGR_ALTR_JTAG			0xd0
+#define CLKMGR_ALTR_EMACACTR			0xd4
+#define CLKMGR_ALTR_EMACBCTR			0xd8
+#define CLKMGR_ALTR_EMACPTPCTR			0xdc
+#define CLKMGR_ALTR_GPIODBCTR			0xe0
+#define CLKMGR_ALTR_SDMMCCTR			0xe4
+#define CLKMGR_ALTR_S2FUSER0CTR			0xe8
+#define CLKMGR_ALTR_S2FUSER1CTR			0xec
+#define CLKMGR_ALTR_PSIREFCTR			0xf0
+#define CLKMGR_ALTR_EXTCNTRST			0xf4
+
+#define CLKMGR_CTRL_BOOTMODE			BIT(0)
+
+#define CLKMGR_STAT_BUSY			BIT(0)
+#define CLKMGR_STAT_MAINPLL_LOCKED		BIT(8)
+#define CLKMGR_STAT_MAIN_TRANS			BIT(9)
+#define CLKMGR_STAT_PERPLL_LOCKED		BIT(16)
+#define CLKMGR_STAT_PERF_TRANS			BIT(17)
+#define CLKMGR_STAT_BOOTMODE			BIT(24)
+#define CLKMGR_STAT_BOOTCLKSRC			BIT(25)
+
+#define CLKMGR_STAT_ALLPLL_LOCKED_MASK		\
+	(CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK		0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK		0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK		0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK		0x00000008
+
+#define CLKMGR_CLKSRC_MASK			GENMASK(18, 16)
+#define CLKMGR_CLKSRC_OFFSET			16
+#define CLKMGR_CLKSRC_MAIN			0
+#define CLKMGR_CLKSRC_PER			1
+#define CLKMGR_CLKSRC_OSC1			2
+#define CLKMGR_CLKSRC_INTOSC			3
+#define CLKMGR_CLKSRC_FPGA			4
+#define CLKMGR_CLKCNT_MSK			GENMASK(10, 0)
+
+#define CLKMGR_BYPASS_MAINPLL_ALL		0x7
+#define CLKMGR_BYPASS_PERPLL_ALL		0x7f
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET		0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET		8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET		16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET		24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET		26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET		28
+#define CLKMGR_NOCDIV_DIVIDER_MASK		0x3
+
+#define CLKMGR_PLLGLOB_PD_MASK				BIT(0)
+#define CLKMGR_PLLGLOB_RST_MASK				BIT(1)
+#define CLKMGR_PLLGLOB_AREFCLKDIV_MASK			GENMASK(11, 8)
+#define CLKMGR_PLLGLOB_DREFCLKDIV_MASK			GENMASK(13, 12)
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK			GENMASK(13, 8)
+#define CLKMGR_PLLGLOB_MODCLKDIV_MASK			GENMASK(24, 27)
+#define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET		8
+#define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET		12
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET			8
+#define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET			24
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK			GENMASK(17, 16)
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET			16
+#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK		BIT(29)
+
+#define CLKMGR_VCO_PSRC_EOSC1			0
+#define CLKMGR_VCO_PSRC_INTOSC			1
+#define CLKMGR_VCO_PSRC_F2S			2
+
+#define CLKMGR_MEM_REQ_SET_MSK			BIT(24)
+#define CLKMGR_MEM_WR_SET_MSK			BIT(25)
+#define CLKMGR_MEM_ERR_MSK			BIT(26)
+#define CLKMGR_MEM_WDAT_LSB_OFFSET		16
+#define CLKMGR_MEM_ADDR_MASK			GENMASK(15, 0)
+#define CLKMGR_MEM_ADDR_START			0x00004000
+
+#define CLKMGR_PLLCX_EN_SET_MSK			BIT(27)
+#define CLKMGR_PLLCX_MUTE_SET_MSK		BIT(28)
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK		GENMASK(23, 16)
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET		16
+#define CLKMGR_VCOCALIB_HSCNT_MASK		GENMASK(9, 0)
+#define CLKMGR_VCOCALIB_MSCNT_CONST		100
+#define CLKMGR_VCOCALIB_HSCNT_CONST		4
+
+#define CLKMGR_PLLM_MDIV_MASK			GENMASK(9, 0)
+
+#define CLKMGR_LOSTLOCK_SET_MASK		BIT(0)
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		BIT(5)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET	26
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK		BIT(26)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET	27
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK		BIT(27)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET	28
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK		BIT(28)
+
+#define CLKMGR_ALT_EMACCTR_SRC_OFFSET		16
+#define CLKMGR_ALT_EMACCTR_SRC_MASK		GENMASK(18, 16)
+#define CLKMGR_ALT_EMACCTR_CNT_OFFSET		0
+#define CLKMGR_ALT_EMACCTR_CNT_MASK		GENMASK(10, 0)
+
+#define CLKMGR_ALT_EXTCNTRST_EMACACNTRST	BIT(0)
+#define CLKMGR_ALT_EXTCNTRST_EMACBCNTRST	BIT(1)
+#define CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST	BIT(2)
+#define CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST	BIT(3)
+#define CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST	BIT(4)
+#define CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST	BIT(5)
+#define CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST	BIT(6)
+#define CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST	BIT(7)
+#define CLKMGR_ALT_EXTCNTRST_ALLCNTRST		\
+	(CLKMGR_ALT_EXTCNTRST_EMACACNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_EMACBCNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST |	\
+	 CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST)
+#endif /* _CLK_AGILEX_ */
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 2b1c1be3b5..8f590dc5f6 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,8 +1,8 @@
 config SPL_ALTERA_SDRAM
 	bool "SoCFPGA DDR SDRAM driver in SPL"
 	depends on SPL
-	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10
-	select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
-	select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
+	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+	select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+	select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	help
 	  Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 341ac0d73b..39dfee5d5a 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -9,5 +9,6 @@
 ifdef CONFIG_$(SPL_)ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
-obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
 endif
diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c
new file mode 100644
index 0000000000..0cbcd14056
--- /dev/null
+++ b/drivers/ddr/altera/sdram_agilex.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <div64.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <reset.h>
+#include "sdram_soc64.h"
+#include <wait_bit.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int sdram_mmr_init_full(struct udevice *dev)
+{
+	struct altera_sdram_platdata *plat = dev->platdata;
+	struct altera_sdram_priv *priv = dev_get_priv(dev);
+	u32 i;
+	int ret;
+	phys_size_t hw_size;
+	bd_t bd = {0};
+
+	/* Ensure HMC clock is running */
+	if (poll_hmc_clock_status()) {
+		debug("DDR: Error as HMC clock was not running\n");
+		return -EPERM;
+	}
+
+	/* Trying 3 times to do a calibration */
+	for (i = 0; i < 3; i++) {
+		ret = wait_for_bit_le32((const void *)(plat->hmc +
+					DDRCALSTAT),
+					DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
+					false);
+		if (!ret)
+			break;
+
+		emif_reset(plat);
+	}
+
+	if (ret) {
+		puts("DDR: Error as SDRAM calibration failed\n");
+		return -EPERM;
+	}
+	debug("DDR: Calibration success\n");
+
+	/*
+	 * Configure the DDR IO size
+	 * niosreserve0: Used to indicate DDR width &
+	 *	bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
+	 *	bit[8]   = 1 if user-mode OCT is present
+	 *	bit[9]   = 1 if warm reset compiled into EMIF Cal Code
+	 *	bit[10]  = 1 if warm reset is on during generation in EMIF Cal
+	 * niosreserve1: IP ADCDS version encoded as 16 bit value
+	 *	bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
+	 *			    3=EAP, 4-6 are reserved)
+	 *	bit[5:3] = Service Pack # (e.g. 1)
+	 *	bit[9:6] = Minor Release #
+	 *	bit[14:10] = Major Release #
+	 */
+	/* Configure DDR IO size x16, x32 and x64 mode */
+	u32 update_value;
+
+	update_value = hmc_readl(plat, NIOSRESERVED0);
+	update_value = (update_value & 0xFF) >> 5;
+
+	/* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
+	update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
+	hmc_ecc_writel(plat, update_value, DDRIOCTRL);
+
+	/* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
+	hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
+
+	/* assigning the SDRAM size */
+	phys_size_t size = sdram_calculate_size(plat);
+
+	if (size <= 0)
+		hw_size = PHYS_SDRAM_1_SIZE;
+	else
+		hw_size = size;
+
+	/* Get bank configuration from devicetree */
+	ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+				     (phys_size_t *)&gd->ram_size, &bd);
+	if (ret) {
+		puts("DDR: Failed to decode memory node\n");
+		return -ENXIO;
+	}
+
+	if (gd->ram_size != hw_size) {
+		printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
+		       gd->ram_size >> 20);
+		printf(" mismatch with hardware (%lld MiB).\n",
+		       hw_size >> 20);
+	}
+
+	if (gd->ram_size > hw_size) {
+		printf("DDR: Error: DRAM size from device tree is greater\n");
+		printf(" than hardware size.\n");
+		hang();
+	}
+
+	printf("DDR: %lld MiB\n", gd->ram_size >> 20);
+
+	/* This enables nonsecure access to DDR */
+	/* mpuregion0addr_limit */
+	FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
+			      FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
+	FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
+
+	/* nonmpuregion0addr_limit */
+	FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
+			      FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
+
+	/* Enable mpuregion0enable and nonmpuregion0enable */
+	FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
+			      FW_MPU_DDR_SCR_EN_SET);
+
+	u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
+
+	/* Enable or disable the DDR ECC */
+	if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
+		setbits_le32(plat->hmc + ECCCTRL1,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(plat->hmc + ECCCTRL1,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
+		setbits_le32(plat->hmc + ECCCTRL2,
+			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
+			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+		setbits_le32(plat->hmc + ERRINTEN,
+			     DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
+
+		if (!cpu_has_been_warmreset())
+			sdram_init_ecc_bits(&bd);
+	} else {
+		clrbits_le32(plat->hmc + ECCCTRL1,
+			     (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
+			      DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
+		clrbits_le32(plat->hmc + ECCCTRL2,
+			     (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
+			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
+	}
+
+	/* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
+	writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
+
+	sdram_size_check(&bd);
+
+	priv->info.base = bd.bi_dram[0].start;
+	priv->info.size = gd->ram_size;
+
+	debug("DDR: HMC init success\n");
+	return 0;
+}
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 8c8ea19eb9..435f42bc0a 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -40,9 +40,6 @@ struct sdram_prot_rule {
 	u32	hi_prot_id;
 };
 
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
 
 /**
@@ -455,12 +452,14 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
 			SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 	int ret;
 
-	writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
+	writel(rows,
+	       socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
 
 	sdr_load_regs(sdr_ctrl, cfg);
 
 	/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
-	writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
+	writel(cfg->fpgaport_rst,
+	       socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
 
 	/* only enable if the FPGA is programmed */
 	if (fpgamgr_test_fpga_ready()) {
@@ -516,7 +515,8 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
 	 * since the FB specifies we modify ROWBITs to work around SDRAM
 	 * controller issue.
 	 */
-	row = readl(&sysmgr_regs->iswgrp_handoff[4]);
+	row = readl(socfpga_get_sysmgr_addr() +
+		    SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
 	if (row == 0)
 		row = rowbits;
 	/*
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 82d9a13efa..93c15dd18b 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -14,32 +14,15 @@
 #include <reset.h>
 #include "sdram_s10.h"
 #include <wait_bit.h>
-#include <asm/arch/firewall_s10.h>
-#include <asm/arch/system_manager.h>
+#include <asm/arch/firewall.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 
-struct altera_sdram_priv {
-	struct ram_info info;
-	struct reset_ctl_bulk resets;
-};
-
-struct altera_sdram_platdata {
-	void __iomem *hmc;
-	void __iomem *ddr_sch;
-	void __iomem *iomhc;
-};
-
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_system_manager *sysmgr_regs =
-		(void *)SOCFPGA_SYSMGR_ADDRESS;
-
 #define DDR_CONFIG(A, B, C, R)	(((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
 
-#define PGTABLE_OFF	0x4000
-
 /* The followring are the supported configurations */
 u32 ddr_config[] = {
 	/* DDR_CONFIG(Address order,Bank,Column,Row) */
@@ -66,28 +49,6 @@ u32 ddr_config[] = {
 	DDR_CONFIG(1, 4, 10, 17),
 };
 
-static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
-	return readl(plat->iomhc + reg);
-}
-
-static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
-{
-	return readl(plat->hmc + reg);
-}
-
-static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
-			  u32 data, u32 reg)
-{
-	return writel(data, plat->hmc + reg);
-}
-
-static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
-			  u32 reg)
-{
-	return writel(data, plat->ddr_sch + reg);
-}
-
 int match_ddr_conf(u32 ddr_conf)
 {
 	int i;
@@ -99,192 +60,12 @@ int match_ddr_conf(u32 ddr_conf)
 	return 0;
 }
 
-static int emif_clear(struct altera_sdram_platdata *plat)
-{
-	hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
-
-	return wait_for_bit_le32((const void *)(plat->hmc +
-				 RSTHANDSHAKESTAT),
-				 DDR_HMC_RSTHANDSHAKE_MASK,
-				 false, 1000, false);
-}
-
-static int emif_reset(struct altera_sdram_platdata *plat)
-{
-	u32 c2s, s2c, ret;
-
-	c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
-	s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
-
-	debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
-	      c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
-	      hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
-	      hmc_readl(plat, DRAMSTS));
-
-	if (s2c && emif_clear(plat)) {
-		printf("DDR: emif_clear() failed\n");
-		return -1;
-	}
-
-	debug("DDR: Triggerring emif reset\n");
-	hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
-
-	/* if seq2core[3] = 0, we are good */
-	ret = wait_for_bit_le32((const void *)(plat->hmc +
-				 RSTHANDSHAKESTAT),
-				 DDR_HMC_SEQ2CORE_INT_RESP_MASK,
-				 false, 1000, false);
-	if (ret) {
-		printf("DDR: failed to get ack from EMIF\n");
-		return ret;
-	}
-
-	ret = emif_clear(plat);
-	if (ret) {
-		printf("DDR: emif_clear() failed\n");
-		return ret;
-	}
-
-	debug("DDR: %s triggered successly\n", __func__);
-	return 0;
-}
-
-static int poll_hmc_clock_status(void)
-{
-	return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
-				 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
-}
-
-static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
-{
-	phys_size_t i;
-
-	if (addr % CONFIG_SYS_CACHELINE_SIZE) {
-		printf("DDR: address 0x%llx is not cacheline size aligned.\n",
-		       addr);
-		hang();
-	}
-
-	if (size % CONFIG_SYS_CACHELINE_SIZE) {
-		printf("DDR: size 0x%llx is not multiple of cacheline size\n",
-		       size);
-		hang();
-	}
-
-	/* Use DC ZVA instruction to clear memory to zeros by a cache line */
-	for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
-		asm volatile("dc zva, %0"
-		     :
-		     : "r"(addr)
-		     : "memory");
-		addr += CONFIG_SYS_CACHELINE_SIZE;
-	}
-}
-
-static void sdram_init_ecc_bits(bd_t *bd)
-{
-	phys_size_t size, size_init;
-	phys_addr_t start_addr;
-	int bank = 0;
-	unsigned int start = get_timer(0);
-
-	icache_enable();
-
-	start_addr = bd->bi_dram[0].start;
-	size = bd->bi_dram[0].size;
-
-	/* Initialize small block for page table */
-	memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
-	gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
-	gd->arch.tlb_size = PGTABLE_SIZE;
-	start_addr += PGTABLE_SIZE + PGTABLE_OFF;
-	size -= (PGTABLE_OFF + PGTABLE_SIZE);
-	dcache_enable();
-
-	while (1) {
-		while (size) {
-			size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
-			sdram_clear_mem(start_addr, size_init);
-			size -= size_init;
-			start_addr += size_init;
-			WATCHDOG_RESET();
-		}
-
-		bank++;
-		if (bank >= CONFIG_NR_DRAM_BANKS)
-			break;
-
-		start_addr = bd->bi_dram[bank].start;
-		size = bd->bi_dram[bank].size;
-	}
-
-	dcache_disable();
-	icache_disable();
-
-	printf("SDRAM-ECC: Initialized success with %d ms\n",
-	       (unsigned int)get_timer(start));
-}
-
-static void sdram_size_check(bd_t *bd)
-{
-	phys_size_t total_ram_check = 0;
-	phys_size_t ram_check = 0;
-	phys_addr_t start = 0;
-	int bank;
-
-	/* Sanity check ensure correct SDRAM size specified */
-	debug("DDR: Running SDRAM size sanity check\n");
-
-	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		start = bd->bi_dram[bank].start;
-		while (ram_check < bd->bi_dram[bank].size) {
-			ram_check += get_ram_size((void *)(start + ram_check),
-						 (phys_size_t)SZ_1G);
-		}
-		total_ram_check += ram_check;
-		ram_check = 0;
-	}
-
-	/* If the ram_size is 2GB smaller, we can assume the IO space is
-	 * not mapped in.  gd->ram_size is the actual size of the dram
-	 * not the accessible size.
-	 */
-	if (total_ram_check != gd->ram_size) {
-		puts("DDR: SDRAM size check failed!\n");
-		hang();
-	}
-
-	debug("DDR: SDRAM size check passed!\n");
-}
-
-/**
- * sdram_calculate_size() - Calculate SDRAM size
- *
- * Calculate SDRAM device size based on SDRAM controller parameters.
- * Size is specified in bytes.
- */
-static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
-{
-	u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
-
-	phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
-			 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
-			 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
-			 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
-			 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
-
-	size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
-			DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
-
-	return size;
-}
-
 /**
  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  *
  * Initialize the SDRAM MMR.
  */
-static int sdram_mmr_init_full(struct udevice *dev)
+int sdram_mmr_init_full(struct udevice *dev)
 {
 	struct altera_sdram_platdata *plat = dev->platdata;
 	struct altera_sdram_priv *priv = dev_get_priv(dev);
@@ -324,6 +105,20 @@ static int sdram_mmr_init_full(struct udevice *dev)
 	clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 		     CCU_ADBASE_DI_MASK);
 
+	/* Enable access to DDR from TCU */
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
+		     CCU_ADBASE_DI_MASK);
+	clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
+		     CCU_ADBASE_DI_MASK);
+
 	/* this enables nonsecure access to DDR */
 	/* mpuregion0addr_limit */
 	FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
@@ -512,9 +307,6 @@ static int sdram_mmr_init_full(struct udevice *dev)
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 		hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
 
-		/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
-		writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
-
 		/* Initialize memory content if not from warm reset */
 		if (!cpu_has_been_warmreset())
 			sdram_init_ecc_bits(&bd);
@@ -528,6 +320,9 @@ static int sdram_mmr_init_full(struct udevice *dev)
 			      DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 	}
 
+	/* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
+	writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
+
 	sdram_size_check(&bd);
 
 	priv->info.base = bd.bi_dram[0].start;
@@ -537,80 +332,3 @@ static int sdram_mmr_init_full(struct udevice *dev)
 	return 0;
 }
 
-static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
-{
-	struct altera_sdram_platdata *plat = dev->platdata;
-	fdt_addr_t addr;
-
-	addr = dev_read_addr_index(dev, 0);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-	plat->ddr_sch = (void __iomem *)addr;
-
-	addr = dev_read_addr_index(dev, 1);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-	plat->iomhc = (void __iomem *)addr;
-
-	addr = dev_read_addr_index(dev, 2);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-	plat->hmc = (void __iomem *)addr;
-
-	return 0;
-}
-
-static int altera_sdram_probe(struct udevice *dev)
-{
-	int ret;
-	struct altera_sdram_priv *priv = dev_get_priv(dev);
-
-	ret = reset_get_bulk(dev, &priv->resets);
-	if (ret) {
-		dev_err(dev, "Can't get reset: %d\n", ret);
-		return -ENODEV;
-	}
-	reset_deassert_bulk(&priv->resets);
-
-	if (sdram_mmr_init_full(dev) != 0) {
-		puts("SDRAM init failed.\n");
-		goto failed;
-	}
-
-	return 0;
-
-failed:
-	reset_release_bulk(&priv->resets);
-	return -ENODEV;
-}
-
-static int altera_sdram_get_info(struct udevice *dev,
-				 struct ram_info *info)
-{
-	struct altera_sdram_priv *priv = dev_get_priv(dev);
-
-	info->base = priv->info.base;
-	info->size = priv->info.size;
-
-	return 0;
-}
-
-static struct ram_ops altera_sdram_ops = {
-	.get_info = altera_sdram_get_info,
-};
-
-static const struct udevice_id altera_sdram_ids[] = {
-	{ .compatible = "altr,sdr-ctl-s10" },
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(altera_sdram) = {
-	.name = "altr_sdr_ctl",
-	.id = UCLASS_RAM,
-	.of_match = altera_sdram_ids,
-	.ops = &altera_sdram_ops,
-	.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
-	.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
-	.probe = altera_sdram_probe,
-	.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
-};
diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_s10.h
index 096c06cba2..cca4cb35ec 100644
--- a/drivers/ddr/altera/sdram_s10.h
+++ b/drivers/ddr/altera/sdram_s10.h
@@ -11,48 +11,6 @@
 #define DDR_READ_LATENCY_DELAY		40
 #define DDR_ACTIVATE_FAWBANK		0x1
 
-/* ECC HMC registers */
-#define DDRIOCTRL			0x8
-#define DDRCALSTAT			0xc
-#define DRAMADDRWIDTH			0xe0
-#define ECCCTRL1			0x100
-#define ECCCTRL2			0x104
-#define ERRINTEN			0x110
-#define ERRINTENS			0x114
-#define INTMODE				0x11c
-#define INTSTAT				0x120
-#define AUTOWB_CORRADDR			0x138
-#define ECC_REG2WRECCDATABUS		0x144
-#define ECC_DIAGON			0x150
-#define ECC_DECSTAT			0x154
-#define HPSINTFCSEL			0x210
-#define RSTHANDSHAKECTRL		0x214
-#define RSTHANDSHAKESTAT		0x218
-
-#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK		0x00000003
-#define DDR_HMC_DDRCALSTAT_CAL_MSK		BIT(0)
-#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK	BIT(16)
-#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK		BIT(8)
-#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK		BIT(0)
-#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK		BIT(8)
-#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK		BIT(0)
-#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK	BIT(16)
-#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK	BIT(0)
-#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK	BIT(0)
-#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK	BIT(1)
-#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK	BIT(0)
-#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK	BIT(1)
-#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK	BIT(16)
-#define DDR_HMC_INTMODE_INTMODE_SET_MSK		BIT(0)
-#define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
-#define DDR_HMC_CORE2SEQ_INT_REQ		0xF
-#define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
-#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
-
-#define	DDR_HMC_ERRINTEN_INTMASK				\
-		(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |	\
-		 DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
-
 /* NOC DDR scheduler */
 #define DDR_SCH_ID_COREID		0
 #define DDR_SCH_ID_REVID		0x4
@@ -79,110 +37,6 @@
 #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF		2
 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF		4
 
-/* HMC MMR IO48 registers */
-#define CTRLCFG0			0x28
-#define CTRLCFG1			0x2c
-#define DRAMTIMING0			0x50
-#define CALTIMING0			0x7c
-#define CALTIMING1			0x80
-#define CALTIMING2			0x84
-#define CALTIMING3			0x88
-#define CALTIMING4			0x8c
-#define CALTIMING9			0xa0
-#define DRAMADDRW			0xa8
-#define DRAMSTS				0xec
-#define NIOSRESERVED0			0x110
-#define NIOSRESERVED1			0x114
-#define NIOSRESERVED2			0x118
-
-#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)			\
-	(((x) >> 0) & 0x1F)
-#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)			\
-	(((x) >> 5) & 0x1F)
-#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)		\
-	(((x) >> 10) & 0xF)
-#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x)		\
-	(((x) >> 14) & 0x3)
-#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x)			\
-	(((x) >> 16) & 0x7)
-
-#define CTRLCFG0_CFG_MEMTYPE(x)				\
-	(((x) >> 0) & 0xF)
-#define CTRLCFG0_CFG_DIMM_TYPE(x)			\
-	(((x) >> 4) & 0x7)
-#define CTRLCFG0_CFG_AC_POS(x)				\
-	(((x) >> 7) & 0x3)
-#define CTRLCFG0_CFG_CTRL_BURST_LEN(x)			\
-	(((x) >> 9) & 0x1F)
-
-#define CTRLCFG1_CFG_DBC3_BURST_LEN(x)			\
-	(((x) >> 0) & 0x1F)
-#define CTRLCFG1_CFG_ADDR_ORDER(x)			\
-	(((x) >> 5) & 0x3)
-#define CTRLCFG1_CFG_CTRL_EN_ECC(x)			\
-	(((x) >> 7) & 0x1)
-
-#define DRAMTIMING0_CFG_TCL(x)				\
-	(((x) >> 0) & 0x7F)
-
-#define CALTIMING0_CFG_ACT_TO_RDWR(x)			\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_PCH(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_ACT(x)			\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING0_CFG_ACT_TO_ACT_DB(x)			\
-	(((x) >> 18) & 0x3F)
-
-#define CALTIMING1_CFG_RD_TO_RD(x)			\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_RD_DC(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_RD_DB(x)			\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_WR(x)			\
-	(((x) >> 18) & 0x3F)
-#define CALTIMING1_CFG_RD_TO_WR_DC(x)			\
-	(((x) >> 24) & 0x3F)
-
-#define CALTIMING2_CFG_RD_TO_WR_DB(x)			\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING2_CFG_RD_TO_WR_PCH(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING2_CFG_RD_AP_TO_VALID(x)		\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING2_CFG_WR_TO_WR(x)			\
-	(((x) >> 18) & 0x3F)
-#define CALTIMING2_CFG_WR_TO_WR_DC(x)			\
-	(((x) >> 24) & 0x3F)
-
-#define CALTIMING3_CFG_WR_TO_WR_DB(x)			\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD_DC(x)			\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_RD_DB(x)			\
-	(((x) >> 18) & 0x3F)
-#define CALTIMING3_CFG_WR_TO_PCH(x)			\
-	(((x) >> 24) & 0x3F)
-
-#define CALTIMING4_CFG_WR_AP_TO_VALID(x)		\
-	(((x) >> 0) & 0x3F)
-#define CALTIMING4_CFG_PCH_TO_VALID(x)			\
-	(((x) >> 6) & 0x3F)
-#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x)		\
-	(((x) >> 12) & 0x3F)
-#define CALTIMING4_CFG_ARF_TO_VALID(x)			\
-	(((x) >> 18) & 0xFF)
-#define CALTIMING4_CFG_PDN_TO_VALID(x)			\
-	(((x) >> 26) & 0x3F)
-
-#define CALTIMING9_CFG_4_ACT_TO_ACT(x)			\
-	(((x) >> 0) & 0xFF)
-
-/* Firewall DDR scheduler MPFE */
-#define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
-#define FW_HMC_ADAPTOR_MPU_MASK			BIT(0)
+#include "sdram_soc64.h"
 
 #endif /* _SDRAM_S10_H_ */
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
new file mode 100644
index 0000000000..985a108b1c
--- /dev/null
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <div64.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <reset.h>
+#include "sdram_soc64.h"
+#include <wait_bit.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+
+#define PGTABLE_OFF	0x4000
+
+u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
+{
+	return readl(plat->iomhc + reg);
+}
+
+u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
+{
+	return readl(plat->hmc + reg);
+}
+
+u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+		   u32 data, u32 reg)
+{
+	return writel(data, plat->hmc + reg);
+}
+
+u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+		   u32 reg)
+{
+	return writel(data, plat->ddr_sch + reg);
+}
+
+int emif_clear(struct altera_sdram_platdata *plat)
+{
+	hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
+
+	return wait_for_bit_le32((const void *)(plat->hmc +
+				 RSTHANDSHAKESTAT),
+				 DDR_HMC_RSTHANDSHAKE_MASK,
+				 false, 1000, false);
+}
+
+int emif_reset(struct altera_sdram_platdata *plat)
+{
+	u32 c2s, s2c, ret;
+
+	c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
+	s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
+
+	debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
+	      c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
+	      hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
+	      hmc_readl(plat, DRAMSTS));
+
+	if (s2c && emif_clear(plat)) {
+		printf("DDR: emif_clear() failed\n");
+		return -1;
+	}
+
+	debug("DDR: Triggerring emif reset\n");
+	hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
+
+	/* if seq2core[3] = 0, we are good */
+	ret = wait_for_bit_le32((const void *)(plat->hmc +
+				 RSTHANDSHAKESTAT),
+				 DDR_HMC_SEQ2CORE_INT_RESP_MASK,
+				 false, 1000, false);
+	if (ret) {
+		printf("DDR: failed to get ack from EMIF\n");
+		return ret;
+	}
+
+	ret = emif_clear(plat);
+	if (ret) {
+		printf("DDR: emif_clear() failed\n");
+		return ret;
+	}
+
+	debug("DDR: %s triggered successly\n", __func__);
+	return 0;
+}
+
+int poll_hmc_clock_status(void)
+{
+	return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
+				 SYSMGR_SOC64_HMC_CLK),
+				 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
+}
+
+void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
+{
+	phys_size_t i;
+
+	if (addr % CONFIG_SYS_CACHELINE_SIZE) {
+		printf("DDR: address 0x%llx is not cacheline size aligned.\n",
+		       addr);
+		hang();
+	}
+
+	if (size % CONFIG_SYS_CACHELINE_SIZE) {
+		printf("DDR: size 0x%llx is not multiple of cacheline size\n",
+		       size);
+		hang();
+	}
+
+	/* Use DC ZVA instruction to clear memory to zeros by a cache line */
+	for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
+		asm volatile("dc zva, %0"
+		     :
+		     : "r"(addr)
+		     : "memory");
+		addr += CONFIG_SYS_CACHELINE_SIZE;
+	}
+}
+
+void sdram_init_ecc_bits(bd_t *bd)
+{
+	phys_size_t size, size_init;
+	phys_addr_t start_addr;
+	int bank = 0;
+	unsigned int start = get_timer(0);
+
+	icache_enable();
+
+	start_addr = bd->bi_dram[0].start;
+	size = bd->bi_dram[0].size;
+
+	/* Initialize small block for page table */
+	memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
+	gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
+	gd->arch.tlb_size = PGTABLE_SIZE;
+	start_addr += PGTABLE_SIZE + PGTABLE_OFF;
+	size -= (PGTABLE_OFF + PGTABLE_SIZE);
+	dcache_enable();
+
+	while (1) {
+		while (size) {
+			size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
+			sdram_clear_mem(start_addr, size_init);
+			size -= size_init;
+			start_addr += size_init;
+			WATCHDOG_RESET();
+		}
+
+		bank++;
+		if (bank >= CONFIG_NR_DRAM_BANKS)
+			break;
+
+		start_addr = bd->bi_dram[bank].start;
+		size = bd->bi_dram[bank].size;
+	}
+
+	dcache_disable();
+	icache_disable();
+
+	printf("SDRAM-ECC: Initialized success with %d ms\n",
+	       (unsigned int)get_timer(start));
+}
+
+void sdram_size_check(bd_t *bd)
+{
+	phys_size_t total_ram_check = 0;
+	phys_size_t ram_check = 0;
+	phys_addr_t start = 0;
+	int bank;
+
+	/* Sanity check ensure correct SDRAM size specified */
+	debug("DDR: Running SDRAM size sanity check\n");
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start = bd->bi_dram[bank].start;
+		while (ram_check < bd->bi_dram[bank].size) {
+			ram_check += get_ram_size((void *)(start + ram_check),
+						 (phys_size_t)SZ_1G);
+		}
+		total_ram_check += ram_check;
+		ram_check = 0;
+	}
+
+	/* If the ram_size is 2GB smaller, we can assume the IO space is
+	 * not mapped in.  gd->ram_size is the actual size of the dram
+	 * not the accessible size.
+	 */
+	if (total_ram_check != gd->ram_size) {
+		puts("DDR: SDRAM size check failed!\n");
+		hang();
+	}
+
+	debug("DDR: SDRAM size check passed!\n");
+}
+
+/**
+ * sdram_calculate_size() - Calculate SDRAM size
+ *
+ * Calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ */
+phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
+{
+	u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
+
+	phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+			 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
+			 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
+			 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
+			 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
+
+	size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
+			DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
+
+	return size;
+}
+
+static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
+{
+	struct altera_sdram_platdata *plat = dev->platdata;
+	fdt_addr_t addr;
+
+	addr = dev_read_addr_index(dev, 0);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->ddr_sch = (void __iomem *)addr;
+
+	addr = dev_read_addr_index(dev, 1);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->iomhc = (void __iomem *)addr;
+
+	addr = dev_read_addr_index(dev, 2);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->hmc = (void __iomem *)addr;
+
+	return 0;
+}
+
+static int altera_sdram_probe(struct udevice *dev)
+{
+	int ret;
+	struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+	ret = reset_get_bulk(dev, &priv->resets);
+	if (ret) {
+		dev_err(dev, "Can't get reset: %d\n", ret);
+		return -ENODEV;
+	}
+	reset_deassert_bulk(&priv->resets);
+
+	if (sdram_mmr_init_full(dev) != 0) {
+		puts("SDRAM init failed.\n");
+		goto failed;
+	}
+
+	return 0;
+
+failed:
+	reset_release_bulk(&priv->resets);
+	return -ENODEV;
+}
+
+static int altera_sdram_get_info(struct udevice *dev,
+				 struct ram_info *info)
+{
+	struct altera_sdram_priv *priv = dev_get_priv(dev);
+
+	info->base = priv->info.base;
+	info->size = priv->info.size;
+
+	return 0;
+}
+
+static struct ram_ops altera_sdram_ops = {
+	.get_info = altera_sdram_get_info,
+};
+
+static const struct udevice_id altera_sdram_ids[] = {
+	{ .compatible = "altr,sdr-ctl-s10" },
+	{ .compatible = "intel,sdr-ctl-agilex" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(altera_sdram) = {
+	.name = "altr_sdr_ctl",
+	.id = UCLASS_RAM,
+	.of_match = altera_sdram_ids,
+	.ops = &altera_sdram_ops,
+	.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
+	.probe = altera_sdram_probe,
+	.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
+};
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
new file mode 100644
index 0000000000..7b25a80ae2
--- /dev/null
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef	_SDRAM_SOC64_H_
+#define	_SDRAM_SOC64_H_
+
+#include <common.h>
+#include <linux/sizes.h>
+
+struct altera_sdram_priv {
+	struct ram_info info;
+	struct reset_ctl_bulk resets;
+};
+
+struct altera_sdram_platdata {
+	void __iomem *hmc;
+	void __iomem *ddr_sch;
+	void __iomem *iomhc;
+};
+
+/* ECC HMC registers */
+#define DDRIOCTRL			0x8
+#define DDRCALSTAT			0xc
+#define DRAMADDRWIDTH			0xe0
+#define ECCCTRL1			0x100
+#define ECCCTRL2			0x104
+#define ERRINTEN			0x110
+#define ERRINTENS			0x114
+#define INTMODE				0x11c
+#define INTSTAT				0x120
+#define AUTOWB_CORRADDR			0x138
+#define ECC_REG2WRECCDATABUS		0x144
+#define ECC_DIAGON			0x150
+#define ECC_DECSTAT			0x154
+#define HPSINTFCSEL			0x210
+#define RSTHANDSHAKECTRL		0x214
+#define RSTHANDSHAKESTAT		0x218
+
+#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK		0x00000003
+#define DDR_HMC_DDRCALSTAT_CAL_MSK		BIT(0)
+#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK	BIT(16)
+#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK		BIT(8)
+#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK		BIT(0)
+#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK		BIT(8)
+#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK		BIT(0)
+#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK	BIT(16)
+#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK	BIT(0)
+#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK	BIT(0)
+#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK	BIT(1)
+#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK	BIT(0)
+#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK	BIT(1)
+#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK	BIT(16)
+#define DDR_HMC_INTMODE_INTMODE_SET_MSK		BIT(0)
+#define DDR_HMC_RSTHANDSHAKE_MASK		0x000000ff
+#define DDR_HMC_CORE2SEQ_INT_REQ		0xF
+#define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
+#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
+
+#define	DDR_HMC_ERRINTEN_INTMASK				\
+		(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK |	\
+		 DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
+
+/* HMC MMR IO48 registers */
+#define CTRLCFG0			0x28
+#define CTRLCFG1			0x2c
+#define CTRLCFG3                        0x34
+#define DRAMTIMING0			0x50
+#define CALTIMING0			0x7c
+#define CALTIMING1			0x80
+#define CALTIMING2			0x84
+#define CALTIMING3			0x88
+#define CALTIMING4			0x8c
+#define CALTIMING9			0xa0
+#define DRAMADDRW			0xa8
+#define DRAMSTS				0xec
+#define NIOSRESERVED0			0x110
+#define NIOSRESERVED1			0x114
+#define NIOSRESERVED2			0x118
+
+#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)			\
+	(((x) >> 0) & 0x1F)
+#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)			\
+	(((x) >> 5) & 0x1F)
+#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x)		\
+	(((x) >> 10) & 0xF)
+#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x)		\
+	(((x) >> 14) & 0x3)
+#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x)			\
+	(((x) >> 16) & 0x7)
+
+#define CTRLCFG0_CFG_MEMTYPE(x)				\
+	(((x) >> 0) & 0xF)
+#define CTRLCFG0_CFG_DIMM_TYPE(x)			\
+	(((x) >> 4) & 0x7)
+#define CTRLCFG0_CFG_AC_POS(x)				\
+	(((x) >> 7) & 0x3)
+#define CTRLCFG0_CFG_CTRL_BURST_LEN(x)			\
+	(((x) >> 9) & 0x1F)
+
+#define CTRLCFG1_CFG_DBC3_BURST_LEN(x)			\
+	(((x) >> 0) & 0x1F)
+#define CTRLCFG1_CFG_ADDR_ORDER(x)			\
+	(((x) >> 5) & 0x3)
+#define CTRLCFG1_CFG_CTRL_EN_ECC(x)			\
+	(((x) >> 7) & 0x1)
+
+#define DRAMTIMING0_CFG_TCL(x)				\
+	(((x) >> 0) & 0x7F)
+
+#define CALTIMING0_CFG_ACT_TO_RDWR(x)			\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_PCH(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_ACT(x)			\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING0_CFG_ACT_TO_ACT_DB(x)			\
+	(((x) >> 18) & 0x3F)
+
+#define CALTIMING1_CFG_RD_TO_RD(x)			\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_RD_DC(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_RD_DB(x)			\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_WR(x)			\
+	(((x) >> 18) & 0x3F)
+#define CALTIMING1_CFG_RD_TO_WR_DC(x)			\
+	(((x) >> 24) & 0x3F)
+
+#define CALTIMING2_CFG_RD_TO_WR_DB(x)			\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING2_CFG_RD_TO_WR_PCH(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING2_CFG_RD_AP_TO_VALID(x)		\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING2_CFG_WR_TO_WR(x)			\
+	(((x) >> 18) & 0x3F)
+#define CALTIMING2_CFG_WR_TO_WR_DC(x)			\
+	(((x) >> 24) & 0x3F)
+
+#define CALTIMING3_CFG_WR_TO_WR_DB(x)			\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD_DC(x)			\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_RD_DB(x)			\
+	(((x) >> 18) & 0x3F)
+#define CALTIMING3_CFG_WR_TO_PCH(x)			\
+	(((x) >> 24) & 0x3F)
+
+#define CALTIMING4_CFG_WR_AP_TO_VALID(x)		\
+	(((x) >> 0) & 0x3F)
+#define CALTIMING4_CFG_PCH_TO_VALID(x)			\
+	(((x) >> 6) & 0x3F)
+#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x)		\
+	(((x) >> 12) & 0x3F)
+#define CALTIMING4_CFG_ARF_TO_VALID(x)			\
+	(((x) >> 18) & 0xFF)
+#define CALTIMING4_CFG_PDN_TO_VALID(x)			\
+	(((x) >> 26) & 0x3F)
+
+#define CALTIMING9_CFG_4_ACT_TO_ACT(x)			\
+	(((x) >> 0) & 0xFF)
+
+/* Firewall DDR scheduler MPFE */
+#define FW_HMC_ADAPTOR_REG_ADDR			0xf8020004
+#define FW_HMC_ADAPTOR_MPU_MASK			BIT(0)
+
+u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg);
+u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg);
+u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+		   u32 data, u32 reg);
+u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+		   u32 reg);
+int emif_clear(struct altera_sdram_platdata *plat);
+int emif_reset(struct altera_sdram_platdata *plat);
+int poll_hmc_clock_status(void);
+void sdram_clear_mem(phys_addr_t addr, phys_size_t size);
+void sdram_init_ecc_bits(bd_t *bd);
+void sdram_size_check(bd_t *bd);
+phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat);
+int sdram_mmr_init_full(struct udevice *dev);
+
+#endif /* _SDRAM_SOC64_H_ */
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5fb9d6a191..2853581b97 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_fpga_manager *fpga_manager_base =
 		(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
 
-static const struct socfpga_system_manager *system_manager_base =
-		(void *)SOCFPGA_SYSMGR_ADDRESS;
-
 static void fpgamgr_set_cd_ratio(unsigned long ratio);
 
 static uint32_t fpgamgr_get_msel(void)
@@ -818,7 +815,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
 	}
 
 	/* Disable all signals from HPS peripheral controller to FPGA */
-	writel(0, &system_manager_base->fpgaintf_en_global);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 
 	/* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
 	socfpga_bridges_reset();
@@ -910,7 +907,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	memset(&rbfinfo, 0, sizeof(rbfinfo));
 
 	/* Disable all signals from hps peripheral controller to fpga */
-	writel(0, &system_manager_base->fpgaintf_en_global);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
 
 	/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
 	socfpga_bridges_reset();
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 6d16e0b37f..d73474f29e 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -15,8 +15,6 @@
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
 	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -214,7 +212,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	/* Prior programming the FPGA, all bridges need to be shut off */
 
 	/* Disable all signals from hps peripheral controller to fpga */
-	writel(0, &sysmgr_regs->fpgaintfgrp_module);
+	writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_FPGAINFGRP_MODULE);
 
 	/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS	0x5080
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 739c1629a2..568a3e77d3 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -18,11 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct socfpga_clock_manager *clock_manager_base =
-		(void *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
-		(void *)SOCFPGA_SYSMGR_ADDRESS;
-
 struct socfpga_dwmci_plat {
 	struct mmc_config cfg;
 	struct mmc mmc;
@@ -56,19 +51,19 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 			 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
 	/* Disable SDMMC clock. */
-	clrbits_le32(&clock_manager_base->per_pll.en,
-		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+	clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+		     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 
 	debug("%s: drvsel %d smplsel %d\n", __func__,
 	      priv->drvsel, priv->smplsel);
-	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
+	writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
-		readl(&system_manager_base->sdmmcgrp_ctrl));
+		readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
 
 	/* Enable SDMMC clock */
-	setbits_le32(&clock_manager_base->per_pll.en,
-		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
+		     CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
 }
 
 static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
index d6c26a5b23..3390b7bdc2 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -12,7 +12,7 @@
 #include <asm/arch/reset_manager.h>
 
 struct socfpga_sysreset_data {
-	struct socfpga_reset_manager *rstmgr_base;
+	void __iomem *rstmgr_base;
 };
 
 static int socfpga_sysreset_request(struct udevice *dev,
@@ -23,11 +23,11 @@ static int socfpga_sysreset_request(struct udevice *dev,
 	switch (type) {
 	case SYSRESET_WARM:
 		writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
-		       &data->rstmgr_base->ctrl);
+		       data->rstmgr_base + RSTMGR_CTRL);
 		break;
 	case SYSRESET_COLD:
 		writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
-		       &data->rstmgr_base->ctrl);
+		       data->rstmgr_base + RSTMGR_CTRL);
 		break;
 	default:
 		return -EPROTONOSUPPORT;