Merge branch '2020-10-22-misc-changes'

- Assorted updates for Xen, IPQ40xx, ASpeed, Keymile
- Assorted typo / documentation fixes
- Fix default preboot cmd to act like before with USB_STORAGE set
- A number of other bugfixes throughout the code

48 files changed, 1338 insertions, 244 deletions

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 7a5ee7a45f..f1becd20d8 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -150,32 +150,8 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
 	return 0;
 }
 
-static ulong clk_mux_get_rate(struct clk *clk)
-{
-	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
-			dev_get_clk_ptr(clk->dev) : clk);
-	struct udevice *parent;
-	struct clk *pclk;
-	int err, index;
-
-	index = clk_mux_get_parent(clk);
-	if (index >= mux->num_parents)
-		return -EFAULT;
-
-	err = uclass_get_device_by_name(UCLASS_CLK, mux->parent_names[index],
-					&parent);
-	if (err)
-		return err;
-
-	pclk = dev_get_clk_ptr(parent);
-	if (!pclk)
-		return -ENODEV;
-
-	return clk_get_rate(pclk);
-}
-
 const struct clk_ops clk_mux_ops = {
-	.get_rate = clk_mux_get_rate,
+	.get_rate = clk_generic_get_rate,
 	.set_parent = clk_mux_set_parent,
 };
 
diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index 509b09845a..567d0a4b50 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -142,7 +142,7 @@ int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
 
 	ret = uclass_first_device_drvdata(UCLASS_SYSCON, driver_data, devp);
 	if (ret)
-		return log_msg_ret("find", ret);
+		return ret;
 
 	return 0;
 }
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 84139b85c3..c02badd4a8 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -705,7 +705,7 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 
 	/* Compute it once normally. */
 #ifdef CONFIG_FSL_DDR_INTERACTIVE
-	if (tstc() && (getc() == 'd')) {	/* we got a key press of 'd' */
+	if (tstc() && (getchar() == 'd')) {	/* we got a key press of 'd' */
 		total_memory = fsl_ddr_interactive(pinfo, 0);
 	} else if (fsl_ddr_interactive_env_var_exists()) {
 		total_memory = fsl_ddr_interactive(pinfo, 1);
diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
index 5bf3239921..ac9250f74e 100644
--- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
+++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
@@ -107,7 +107,7 @@
 #define MV_NO_RESOURCE	(0x13)	/* Resource not available (memory ...)   */
 #define MV_FULL		(0x14)	/* Item is full (Queue or table etc...)  */
 #define MV_EMPTY	(0x15)	/* Item is empty (Queue or table etc...) */
-#define MV_INIT_ERROR	(0x16)	/* Error occured while INIT process      */
+#define MV_INIT_ERROR	(0x16)	/* Error occurred while INIT process     */
 #define MV_HW_ERROR	(0x17)	/* Hardware error                        */
 #define MV_TX_ERROR	(0x18)	/* Transmit operation not succeeded      */
 #define MV_RX_ERROR	(0x19)	/* Recieve operation not succeeded       */
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 569a5d39b4..791f32e971 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -807,8 +807,8 @@ int designware_i2c_probe(struct udevice *bus)
 		return -ENXIO;
 	}
 
-	log_info("I2C bus %s version %#x\n", bus->name,
-		 readl(&priv->regs->comp_version));
+	log_debug("I2C bus %s version %#x\n", bus->name,
+		  readl(&priv->regs->comp_version));
 
 	return __dw_i2c_init(priv->regs, 0, 0);
 }
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index c46fa4efc5..a47700e313 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2192,7 +2192,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
 				return 0;
 error:
 			mmc_set_signal_voltage(mmc, old_voltage);
-			/* if an error occured, revert to a safer bus mode */
+			/* if an error occurred, revert to a safer bus mode */
 			mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
 				   EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
 			mmc_select_mode(mmc, MMC_LEGACY);
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 30fe7a0aa2..4f9fa7d0ec 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -1171,7 +1171,7 @@ skip_fall:
 			internal_delay |= (1 << i);
 	}
 
-	dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
+	dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay);
 
 	internal_delay_phase = get_best_delay(dev, host, internal_delay);
 	clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
@@ -1179,7 +1179,7 @@ skip_fall:
 			MSDC_PAD_TUNE_CMDRRDLY_S);
 
 skip_internal:
-	dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+	dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay);
 	return final_delay == 0xff ? -EIO : 0;
 }
 
@@ -1265,7 +1265,7 @@ skip_fall:
 				host->hs200_write_int_delay <<
 				MSDC_PAD_TUNE_DATWRDLY_S);
 
-	dev_err(dev, "Final data pad delay: %x\n", final_delay);
+	dev_dbg(dev, "Final data pad delay: %x\n", final_delay);
 
 	return final_delay == 0xff ? -EIO : 0;
 }
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 2beec2da41..3a5e036880 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -732,6 +732,13 @@ config MDIO_MUX_I2CREG
 	  an I2C chip.  The board it was developed for uses a mux controlled by
 	  on-board FPGA which in turn is accessed as a chip over I2C.
 
+config MDIO_IPQ4019
+	bool "Qualcomm IPQ4019 MDIO interface support"
+	depends on DM_MDIO
+	help
+	  This driver supports the MDIO interface found in Qualcomm
+	  IPQ40xx series Soc-s.
+
 config MVMDIO
 	bool "Marvell MDIO interface support"
 	depends on DM_MDIO
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 9f7a79ecb1..e3bdda359d 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_LAN91C96) += lan91c96.o
 obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
 obj-$(CONFIG_MACB) += macb.o
 obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
+obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
 obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
 obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
 obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
diff --git a/drivers/net/mdio-ipq4019.c b/drivers/net/mdio-ipq4019.c
new file mode 100644
index 0000000000..bc68e1d506
--- /dev/null
+++ b/drivers/net/mdio-ipq4019.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm IPQ4019 MDIO driver
+ *
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/iopoll.h>
+#include <miiphy.h>
+#include <phy.h>
+
+#define MDIO_MODE_REG               0x40
+#define MDIO_ADDR_REG               0x44
+#define MDIO_DATA_WRITE_REG         0x48
+#define MDIO_DATA_READ_REG          0x4c
+#define MDIO_CMD_REG                0x50
+#define MDIO_CMD_ACCESS_BUSY        BIT(16)
+#define MDIO_CMD_ACCESS_START       BIT(8)
+#define MDIO_CMD_ACCESS_CODE_READ   0
+#define MDIO_CMD_ACCESS_CODE_WRITE  1
+
+/* 0 = Clause 22, 1 = Clause 45 */
+#define MDIO_MODE_BIT               BIT(8)
+
+#define IPQ4019_MDIO_TIMEOUT    10000
+#define IPQ4019_MDIO_SLEEP      10
+
+struct ipq4019_mdio_priv {
+	phys_addr_t mdio_base;
+};
+
+static int ipq4019_mdio_wait_busy(struct ipq4019_mdio_priv *priv)
+{
+	unsigned int busy;
+
+	return readl_poll_sleep_timeout(priv->mdio_base + MDIO_CMD_REG, busy,
+				  (busy & MDIO_CMD_ACCESS_BUSY) == 0, IPQ4019_MDIO_SLEEP,
+				  IPQ4019_MDIO_TIMEOUT);
+}
+
+int ipq4019_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+	struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
+	unsigned int cmd;
+
+	if (ipq4019_mdio_wait_busy(priv))
+		return -ETIMEDOUT;
+
+	/* Issue the phy address and reg */
+	writel((addr << 8) | reg, priv->mdio_base + MDIO_ADDR_REG);
+
+	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
+
+	/* Issue read command */
+	writel(cmd, priv->mdio_base + MDIO_CMD_REG);
+
+	/* Wait read complete */
+	if (ipq4019_mdio_wait_busy(priv))
+		return -ETIMEDOUT;
+
+	/* Read and return data */
+	return readl(priv->mdio_base + MDIO_DATA_READ_REG);
+}
+
+int ipq4019_mdio_write(struct udevice *dev, int addr, int devad,
+					  int reg, u16 val)
+{
+	struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
+	unsigned int cmd;
+
+	if (ipq4019_mdio_wait_busy(priv))
+		return -ETIMEDOUT;
+
+	/* Issue the phy addreass and reg */
+	writel((addr << 8) | reg, priv->mdio_base + MDIO_ADDR_REG);
+
+	/* Issue write data */
+	writel(val, priv->mdio_base + MDIO_DATA_WRITE_REG);
+
+	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
+
+	/* Issue write command */
+	writel(cmd, priv->mdio_base + MDIO_CMD_REG);
+
+	/* Wait for write complete */
+
+	if (ipq4019_mdio_wait_busy(priv))
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static const struct mdio_ops ipq4019_mdio_ops = {
+	.read = ipq4019_mdio_read,
+	.write = ipq4019_mdio_write,
+};
+
+static int ipq4019_mdio_bind(struct udevice *dev)
+{
+	if (ofnode_valid(dev->node))
+		device_set_name(dev, ofnode_get_name(dev->node));
+
+	return 0;
+}
+
+static int ipq4019_mdio_probe(struct udevice *dev)
+{
+	struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
+	unsigned int data;
+
+	priv->mdio_base = dev_read_addr(dev);
+	if (priv->mdio_base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	/* Enter Clause 22 mode */
+	data = readl(priv->mdio_base + MDIO_MODE_REG);
+	data &= ~MDIO_MODE_BIT;
+	writel(data, priv->mdio_base + MDIO_MODE_REG);
+
+	return 0;
+}
+
+static const struct udevice_id ipq4019_mdio_ids[] = {
+	{ .compatible = "qcom,ipq4019-mdio", },
+	{ }
+};
+
+U_BOOT_DRIVER(ipq4019_mdio) = {
+	.name           = "ipq4019_mdio",
+	.id             = UCLASS_MDIO,
+	.of_match       = ipq4019_mdio_ids,
+	.bind           = ipq4019_mdio_bind,
+	.probe          = ipq4019_mdio_probe,
+	.ops            = &ipq4019_mdio_ops,
+	.priv_auto_alloc_size   = sizeof(struct ipq4019_mdio_priv),
+};
diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c
index 38390c0d55..5a5d067046 100644
--- a/drivers/ram/stm32mp1/stm32mp1_interactive.c
+++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c
@@ -394,7 +394,7 @@ bool stm32mp1_ddr_interactive(void *priv,
 		unsigned long start = get_timer(0);
 
 		while (1) {
-			if (tstc() && (getc() == 'd')) {
+			if (tstc() && (getchar() == 'd')) {
 				next_step = STEP_DDR_RESET;
 				break;
 			}
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index b60e11f98b..33c2736554 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -72,15 +72,14 @@ config RESET_UNIPHIER
 	  Say Y if you want to control reset signals provided by System Control
 	  block, Media I/O block, Peripheral Block.
 
-config AST2500_RESET
+config RESET_AST2500
 	bool "Reset controller driver for AST2500 SoCs"
-	depends on DM_RESET && WDT_ASPEED
+	depends on DM_RESET
 	default y if ASPEED_AST2500
 	help
-	  Support for reset controller on AST2500 SoC. This controller uses
-	  watchdog to reset different peripherals and thus only supports
-	  resets that are supported by watchdog. The main limitation though
-	  is that some reset signals, like I2C or MISC reset multiple devices.
+	  Support for reset controller on AST2500 SoC.
+	  Say Y if you want to control reset signals of different peripherals
+	  through System Control Unit (SCU).
 
 config RESET_ROCKCHIP
 	bool "Reset controller driver for Rockchip SoCs"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 10a7973f82..fa52aa3329 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -14,7 +14,7 @@ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
-obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
+obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
 obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
deleted file mode 100644
index beb5cd8fa8..0000000000
--- a/drivers/reset/ast2500-reset.c
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2017 Google, Inc
- */
-
-#include <common.h>
-#include <dm.h>
-#include <log.h>
-#include <misc.h>
-#include <reset.h>
-#include <reset-uclass.h>
-#include <wdt.h>
-#include <asm/io.h>
-#include <asm/arch/scu_ast2500.h>
-#include <asm/arch/wdt.h>
-
-struct ast2500_reset_priv {
-	/* WDT used to perform resets. */
-	struct udevice *wdt;
-	struct ast2500_scu *scu;
-};
-
-static int ast2500_ofdata_to_platdata(struct udevice *dev)
-{
-	struct ast2500_reset_priv *priv = dev_get_priv(dev);
-	int ret;
-
-	ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
-					   &priv->wdt);
-	if (ret) {
-		debug("%s: can't find WDT for reset controller", __func__);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
-{
-	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
-	u32 reset_mode, reset_mask;
-	bool reset_sdram;
-	int ret;
-
-	/*
-	 * To reset SDRAM, a specifal flag in SYSRESET register
-	 * needs to be enabled first
-	 */
-	reset_mode = ast_reset_mode_from_flags(reset_ctl->id);
-	reset_mask = ast_reset_mask_from_flags(reset_ctl->id);
-	reset_sdram = reset_mode == WDT_CTRL_RESET_SOC &&
-		(reset_mask & WDT_RESET_SDRAM);
-
-	if (reset_sdram) {
-		ast_scu_unlock(priv->scu);
-		setbits_le32(&priv->scu->sysreset_ctrl1,
-			     SCU_SYSRESET_SDRAM_WDT);
-		ret = wdt_expire_now(priv->wdt, reset_ctl->id);
-		clrbits_le32(&priv->scu->sysreset_ctrl1,
-			     SCU_SYSRESET_SDRAM_WDT);
-		ast_scu_lock(priv->scu);
-	} else {
-		ret = wdt_expire_now(priv->wdt, reset_ctl->id);
-	}
-
-	return ret;
-}
-
-static int ast2500_reset_request(struct reset_ctl *reset_ctl)
-{
-	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
-	      reset_ctl->dev, reset_ctl->id);
-
-	return 0;
-}
-
-static int ast2500_reset_probe(struct udevice *dev)
-{
-	struct ast2500_reset_priv *priv = dev_get_priv(dev);
-
-	priv->scu = ast_get_scu();
-
-	return 0;
-}
-
-static const struct udevice_id ast2500_reset_ids[] = {
-	{ .compatible = "aspeed,ast2500-reset" },
-	{ }
-};
-
-struct reset_ops ast2500_reset_ops = {
-	.rst_assert = ast2500_reset_assert,
-	.request = ast2500_reset_request,
-};
-
-U_BOOT_DRIVER(ast2500_reset) = {
-	.name		= "ast2500_reset",
-	.id		= UCLASS_RESET,
-	.of_match = ast2500_reset_ids,
-	.probe = ast2500_reset_probe,
-	.ops = &ast2500_reset_ops,
-	.ofdata_to_platdata = ast2500_ofdata_to_platdata,
-	.priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
-};
diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
new file mode 100644
index 0000000000..e7b5c7deca
--- /dev/null
+++ b/drivers/reset/reset-ast2500.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 Google, Inc
+ * Copyright 2020 ASPEED Technology Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <misc.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/arch/scu_ast2500.h>
+
+struct ast2500_reset_priv {
+	struct ast2500_scu *scu;
+};
+
+static int ast2500_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int ast2500_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		setbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+	else
+		setbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+	return 0;
+}
+
+static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		clrbits_le32(&scu->sysreset_ctrl1, BIT(reset_ctl->id));
+	else
+		clrbits_le32(&scu->sysreset_ctrl2, BIT(reset_ctl->id - 32));
+
+	return 0;
+}
+
+static int ast2500_reset_probe(struct udevice *dev)
+{
+	int rc;
+	struct ast2500_reset_priv *priv = dev_get_priv(dev);
+	struct udevice *scu_dev;
+
+	/* get SCU base from clock device */
+	rc = uclass_get_device_by_driver(UCLASS_CLK,
+					 DM_GET_DRIVER(aspeed_ast2500_scu), &scu_dev);
+	if (rc) {
+		debug("%s: clock device not found, rc=%d\n", __func__, rc);
+		return rc;
+	}
+
+	priv->scu = devfdt_get_addr_ptr(scu_dev);
+	if (IS_ERR_OR_NULL(priv->scu)) {
+		debug("%s: invalid SCU base pointer\n", __func__);
+		return PTR_ERR(priv->scu);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id ast2500_reset_ids[] = {
+	{ .compatible = "aspeed,ast2500-reset" },
+	{ }
+};
+
+struct reset_ops ast2500_reset_ops = {
+	.request = ast2500_reset_request,
+	.rfree = ast2500_reset_free,
+	.rst_assert = ast2500_reset_assert,
+	.rst_deassert = ast2500_reset_deassert,
+};
+
+U_BOOT_DRIVER(ast2500_reset) = {
+	.name = "ast2500_reset",
+	.id = UCLASS_RESET,
+	.of_match = ast2500_reset_ids,
+	.probe = ast2500_reset_probe,
+	.ops = &ast2500_reset_ops,
+	.priv_auto_alloc_size = sizeof(struct ast2500_reset_priv),
+};
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index e4b22d79eb..11001c8ae7 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -24,6 +24,13 @@ config RNG_SANDBOX
 	  Enable random number generator for sandbox. This is an
 	  emulation of a rng device.
 
+config RNG_MSM
+	bool "Qualcomm SoCs Random Number Generator support"
+	depends on DM_RNG
+	help
+	  This driver provides support for the Random Number
+	  Generator hardware found on Qualcomm SoCs.
+
 config RNG_STM32MP1
 	bool "Enable random number generator for STM32MP1"
 	depends on ARCH_STM32MP
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 44a0003917..8953406882 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -6,5 +6,6 @@
 obj-$(CONFIG_DM_RNG) += rng-uclass.o
 obj-$(CONFIG_RNG_MESON) += meson-rng.o
 obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
+obj-$(CONFIG_RNG_MSM) += msm_rng.o
 obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
 obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
diff --git a/drivers/rng/msm_rng.c b/drivers/rng/msm_rng.c
new file mode 100644
index 0000000000..d51119303a
--- /dev/null
+++ b/drivers/rng/msm_rng.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PRNG driver for Qualcomm IPQ40xx
+ *
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ * Based on Linux driver
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <rng.h>
+
+/* Device specific register offsets */
+#define PRNG_DATA_OUT		0x0000
+#define PRNG_STATUS			0x0004
+#define PRNG_LFSR_CFG		0x0100
+#define PRNG_CONFIG			0x0104
+
+/* Device specific register masks and config values */
+#define PRNG_LFSR_CFG_MASK		0x0000ffff
+#define PRNG_LFSR_CFG_CLOCKS	0x0000dddd
+#define PRNG_CONFIG_HW_ENABLE	BIT(1)
+#define PRNG_STATUS_DATA_AVAIL	BIT(0)
+
+#define MAX_HW_FIFO_DEPTH		16
+#define MAX_HW_FIFO_SIZE		(MAX_HW_FIFO_DEPTH * 4)
+#define WORD_SZ					4
+
+struct msm_rng_priv {
+	phys_addr_t base;
+	struct clk clk;
+};
+
+static int msm_rng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+	size_t currsize = 0;
+	u32 *retdata = data;
+	size_t maxsize;
+	u32 val;
+
+	/* calculate max size bytes to transfer back to caller */
+	maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
+
+	/* read random data from hardware */
+	do {
+		val = readl_relaxed(priv->base + PRNG_STATUS);
+		if (!(val & PRNG_STATUS_DATA_AVAIL))
+			break;
+
+		val = readl_relaxed(priv->base + PRNG_DATA_OUT);
+		if (!val)
+			break;
+
+		*retdata++ = val;
+		currsize += WORD_SZ;
+
+		/* make sure we stay on 32bit boundary */
+		if ((maxsize - currsize) < WORD_SZ)
+			break;
+	} while (currsize < maxsize);
+
+	return 0;
+}
+
+static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
+{
+	u32 val;
+
+	if (enable) {
+		/* Enable PRNG only if it is not already enabled */
+		val = readl_relaxed(priv->base + PRNG_CONFIG);
+		if (val & PRNG_CONFIG_HW_ENABLE) {
+			val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
+			val &= ~PRNG_LFSR_CFG_MASK;
+			val |= PRNG_LFSR_CFG_CLOCKS;
+			writel(val, priv->base + PRNG_LFSR_CFG);
+
+			val = readl_relaxed(priv->base + PRNG_CONFIG);
+			val |= PRNG_CONFIG_HW_ENABLE;
+			writel(val, priv->base + PRNG_CONFIG);
+		}
+	} else {
+		val = readl_relaxed(priv->base + PRNG_CONFIG);
+		val &= ~PRNG_CONFIG_HW_ENABLE;
+		writel(val, priv->base + PRNG_CONFIG);
+	}
+
+	return 0;
+}
+
+static int msm_rng_probe(struct udevice *dev)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+
+	int ret;
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret < 0)
+		return ret;
+
+	return msm_rng_enable(priv, 1);
+}
+
+static int msm_rng_remove(struct udevice *dev)
+{
+	struct msm_rng_priv *priv = dev_get_priv(dev);
+
+	return msm_rng_enable(priv, 0);
+}
+
+static const struct dm_rng_ops msm_rng_ops = {
+	.read = msm_rng_read,
+};
+
+static const struct udevice_id msm_rng_match[] = {
+	{ .compatible = "qcom,prng", },
+	{},
+};
+
+U_BOOT_DRIVER(msm_rng) = {
+	.name = "msm-rng",
+	.id = UCLASS_RNG,
+	.of_match = msm_rng_match,
+	.ops = &msm_rng_ops,
+	.probe = msm_rng_probe,
+	.remove = msm_rng_remove,
+	.priv_auto_alloc_size = sizeof(struct msm_rng_priv),
+};
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 59e2fc44ba..63662001c2 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -75,6 +75,12 @@ config RTC_ISL1208
 	  This driver supports reading and writing the RTC/calendar and detects
 	  total power failures.
 
+config RTC_PCF8563
+	tristate "Philips PCF8563"
+	help
+	  If you say yes here you get support for the Philips PCF8563 RTC
+	  and compatible chips.
+
 config RTC_RV3029
 	bool "Enable RV3029 driver"
 	depends on DM_RTC
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b4805a2e4e..b6ba702bd3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -401,11 +401,19 @@ config DEBUG_UART_MTK
 	  driver will be available until the real driver model serial is
 	  running.
 
+config DEBUG_UART_XEN
+	bool "XEN Hypervisor Console"
+	depends on XEN_SERIAL
+	help
+	  Select this to enable a debug UART using the serial_xen driver. You
+	  will not have to provide any parameters to make this work. The driver
+          will be available until the real driver-model serial is running.
+
 endchoice
 
 config DEBUG_UART_BASE
 	hex "Base address of UART"
-	depends on DEBUG_UART
+	depends on DEBUG_UART && !DEBUG_UART_XEN
 	default 0 if DEBUG_UART_SANDBOX
 	help
 	  This is the base address of your UART for memory-mapped UARTs.
@@ -415,7 +423,7 @@ config DEBUG_UART_BASE
 
 config DEBUG_UART_CLOCK
 	int "UART input clock"
-	depends on DEBUG_UART
+	depends on DEBUG_UART && !DEBUG_UART_XEN
 	default 0 if DEBUG_UART_SANDBOX
 	help
 	  The UART input clock determines the speed of the internal UART
@@ -427,7 +435,7 @@ config DEBUG_UART_CLOCK
 
 config DEBUG_UART_SHIFT
 	int "UART register shift"
-	depends on DEBUG_UART
+	depends on DEBUG_UART && !DEBUG_UART_XEN
 	default 0 if DEBUG_UART
 	help
 	  Some UARTs (notably ns16550) support different register layouts
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 0027625ebf..f3c25d4216 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -413,7 +413,7 @@ static int on_baudrate(const char *name, const char *value, enum env_op op,
 
 		if ((flags & H_INTERACTIVE) != 0)
 			while (1) {
-				if (getc() == '\r')
+				if (getchar() == '\r')
 					break;
 			}
 
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 53358acb81..355659ba05 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -90,7 +90,7 @@ static int on_baudrate(const char *name, const char *value, enum env_op op,
 
 		if ((flags & H_INTERACTIVE) != 0)
 			while (1) {
-				if (getc() == '\r')
+				if (getchar() == '\r')
 					break;
 			}
 
diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c
index ba6504b947..34c90ece40 100644
--- a/drivers/serial/serial_xen.c
+++ b/drivers/serial/serial_xen.c
@@ -5,6 +5,7 @@
  */
 #include <common.h>
 #include <cpu_func.h>
+#include <debug_uart.h>
 #include <dm.h>
 #include <serial.h>
 #include <watchdog.h>
@@ -15,11 +16,14 @@
 #include <xen/events.h>
 
 #include <xen/interface/sched.h>
+#include <xen/interface/xen.h>
 #include <xen/interface/hvm/hvm_op.h>
 #include <xen/interface/hvm/params.h>
 #include <xen/interface/io/console.h>
 #include <xen/interface/io/ring.h>
 
+#include <asm/xen/hypercall.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 u32 console_evtchn;
@@ -175,8 +179,22 @@ U_BOOT_DRIVER(serial_xen) = {
 	.priv_auto_alloc_size	= sizeof(struct xen_uart_priv),
 	.probe			= xen_serial_probe,
 	.ops			= &xen_serial_ops,
-#if !CONFIG_IS_ENABLED(OF_CONTROL)
 	.flags			= DM_FLAG_PRE_RELOC,
-#endif
 };
 
+#if defined(CONFIG_DEBUG_UART_XEN)
+static inline void _debug_uart_init(void) {}
+
+static inline void _debug_uart_putc(int c)
+{
+#if CONFIG_IS_ENABLED(ARM)
+	xen_debug_putc(c);
+#else
+	/* the type cast should work on LE only */
+	HYPERVISOR_console_io(CONSOLEIO_write, 1, (char *)&ch);
+#endif
+}
+
+DEBUG_UART_FUNCS
+
+#endif
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5df97c80fa..f7a9852565 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -271,6 +271,16 @@ config PL022_SPI
 	  controller. If you have an embedded system with an AMBA(R)
 	  bus and a PL022 controller, say Y or M here.
 
+config SPI_QUP
+	bool "Qualcomm SPI controller with QUP interface"
+	depends on ARCH_IPQ40XX
+	help
+	  Qualcomm Universal Peripheral (QUP) core is an AHB slave that
+	  provides a common data path (an output FIFO and an input FIFO)
+	  for serial peripheral interface (SPI) mini-core. SPI in master
+	  mode supports up to 50MHz, up to four chip selects, programmable
+	  data path from 4 bits to 32 bits and numerous protocol variants.
+
 config RENESAS_RPC_SPI
 	bool "Renesas RPC SPI driver"
 	depends on RCAR_GEN3 || RZA1
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index b5c9ff1af8..d9b5bd9b79 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
 obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
 obj-$(CONFIG_PL022_SPI) += pl022_spi.o
+obj-$(CONFIG_SPI_QUP) += spi-qup.o
 obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
 obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
 obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
new file mode 100644
index 0000000000..6f8df55fa5
--- /dev/null
+++ b/drivers/spi/spi-qup.c
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Qualcomm QUP SPI controller
+ * FIFO and Block modes supported, no DMA
+ * mode support
+ *
+ * Copyright (c) 2020 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
+ *
+ * Based on stock U-boot and Linux drivers
+ */
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/delay.h>
+#include <spi.h>
+
+#define QUP_CONFIG				0x0000
+#define QUP_STATE				0x0004
+#define QUP_IO_M_MODES			0x0008
+#define QUP_SW_RESET			0x000c
+#define QUP_OPERATIONAL			0x0018
+#define QUP_ERROR_FLAGS			0x001c
+#define QUP_ERROR_FLAGS_EN		0x0020
+#define QUP_OPERATIONAL_MASK	0x0028
+#define QUP_HW_VERSION			0x0030
+#define QUP_MX_OUTPUT_CNT		0x0100
+#define QUP_OUTPUT_FIFO			0x0110
+#define QUP_MX_WRITE_CNT		0x0150
+#define QUP_MX_INPUT_CNT		0x0200
+#define QUP_MX_READ_CNT			0x0208
+#define QUP_INPUT_FIFO			0x0218
+
+#define SPI_CONFIG				0x0300
+#define SPI_IO_CONTROL			0x0304
+#define SPI_ERROR_FLAGS			0x0308
+#define SPI_ERROR_FLAGS_EN		0x030c
+
+/* QUP_CONFIG fields */
+#define QUP_CONFIG_SPI_MODE			BIT(8)
+#define QUP_CONFIG_CLOCK_AUTO_GATE	BIT(13)
+#define QUP_CONFIG_NO_INPUT			BIT(7)
+#define QUP_CONFIG_NO_OUTPUT		BIT(6)
+#define QUP_CONFIG_N				0x001f
+
+/* QUP_STATE fields */
+#define QUP_STATE_VALID			BIT(2)
+#define QUP_STATE_RESET			0
+#define QUP_STATE_RUN			1
+#define QUP_STATE_PAUSE			3
+#define QUP_STATE_MASK			3
+#define QUP_STATE_CLEAR			2
+
+/* QUP_IO_M_MODES fields */
+#define QUP_IO_M_PACK_EN		BIT(15)
+#define QUP_IO_M_UNPACK_EN		BIT(14)
+#define QUP_IO_M_INPUT_MODE_MASK_SHIFT	12
+#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT	10
+#define QUP_IO_M_INPUT_MODE_MASK	(3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
+#define QUP_IO_M_OUTPUT_MODE_MASK	(3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
+
+#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x)	(((x) & (0x03 << 0)) >> 0)
+#define QUP_IO_M_OUTPUT_FIFO_SIZE(x)	(((x) & (0x07 << 2)) >> 2)
+#define QUP_IO_M_INPUT_BLOCK_SIZE(x)	(((x) & (0x03 << 5)) >> 5)
+#define QUP_IO_M_INPUT_FIFO_SIZE(x)	(((x) & (0x07 << 7)) >> 7)
+
+#define QUP_IO_M_MODE_FIFO		0
+#define QUP_IO_M_MODE_BLOCK		1
+#define QUP_IO_M_MODE_DMOV		2
+#define QUP_IO_M_MODE_BAM		3
+
+/* QUP_OPERATIONAL fields */
+#define QUP_OP_IN_BLOCK_READ_REQ	BIT(13)
+#define QUP_OP_OUT_BLOCK_WRITE_REQ	BIT(12)
+#define QUP_OP_MAX_INPUT_DONE_FLAG	BIT(11)
+#define QUP_OP_MAX_OUTPUT_DONE_FLAG	BIT(10)
+#define QUP_OP_IN_SERVICE_FLAG		BIT(9)
+#define QUP_OP_OUT_SERVICE_FLAG		BIT(8)
+#define QUP_OP_IN_FIFO_FULL		BIT(7)
+#define QUP_OP_OUT_FIFO_FULL		BIT(6)
+#define QUP_OP_IN_FIFO_NOT_EMPTY	BIT(5)
+#define QUP_OP_OUT_FIFO_NOT_EMPTY	BIT(4)
+
+/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
+#define QUP_ERROR_OUTPUT_OVER_RUN	BIT(5)
+#define QUP_ERROR_INPUT_UNDER_RUN	BIT(4)
+#define QUP_ERROR_OUTPUT_UNDER_RUN	BIT(3)
+#define QUP_ERROR_INPUT_OVER_RUN	BIT(2)
+
+/* SPI_CONFIG fields */
+#define SPI_CONFIG_HS_MODE		BIT(10)
+#define SPI_CONFIG_INPUT_FIRST		BIT(9)
+#define SPI_CONFIG_LOOPBACK		BIT(8)
+
+/* SPI_IO_CONTROL fields */
+#define SPI_IO_C_FORCE_CS		BIT(11)
+#define SPI_IO_C_CLK_IDLE_HIGH		BIT(10)
+#define SPI_IO_C_MX_CS_MODE		BIT(8)
+#define SPI_IO_C_CS_N_POLARITY_0	BIT(4)
+#define SPI_IO_C_CS_SELECT(x)		(((x) & 3) << 2)
+#define SPI_IO_C_CS_SELECT_MASK		0x000c
+#define SPI_IO_C_TRISTATE_CS		BIT(1)
+#define SPI_IO_C_NO_TRI_STATE		BIT(0)
+
+/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
+#define SPI_ERROR_CLK_OVER_RUN		BIT(1)
+#define SPI_ERROR_CLK_UNDER_RUN		BIT(0)
+
+#define SPI_NUM_CHIPSELECTS		4
+
+#define SPI_DELAY_THRESHOLD		1
+#define SPI_DELAY_RETRY			10
+
+#define SPI_RESET_STATE			0
+#define SPI_RUN_STATE			1
+#define SPI_CORE_RESET			0
+#define SPI_CORE_RUNNING		1
+
+#define DUMMY_DATA_VAL			0
+#define TIMEOUT_CNT				100
+
+#define QUP_STATE_VALID_BIT				2
+#define QUP_CONFIG_MINI_CORE_MSK		(0x0F << 8)
+#define QUP_CONFIG_MINI_CORE_SPI		BIT(8)
+#define QUP_CONF_INPUT_MSK				BIT(7)
+#define QUP_CONF_INPUT_ENA				(0 << 7)
+#define QUP_CONF_NO_INPUT				BIT(7)
+#define QUP_CONF_OUTPUT_MSK				BIT(6)
+#define QUP_CONF_OUTPUT_ENA				(0 << 6)
+#define QUP_CONF_NO_OUTPUT				BIT(6)
+#define QUP_STATE_RUN_STATE				0x1
+#define QUP_STATE_RESET_STATE			0x0
+#define QUP_STATE_PAUSE_STATE			0x3
+#define SPI_BIT_WORD_MSK				0x1F
+#define SPI_8_BIT_WORD					0x07
+#define LOOP_BACK_MSK					BIT(8)
+#define NO_LOOP_BACK					(0 << 8)
+#define SLAVE_OPERATION_MSK				BIT(5)
+#define SLAVE_OPERATION					(0 << 5)
+#define CLK_ALWAYS_ON					(0 << 9)
+#define MX_CS_MODE						BIT(8)
+#define CS_POLARITY_MASK				BIT(4)
+#define NO_TRI_STATE					BIT(0)
+#define FORCE_CS_MSK					BIT(11)
+#define FORCE_CS_EN						BIT(11)
+#define FORCE_CS_DIS					(0 << 11)
+#define OUTPUT_BIT_SHIFT_MSK			BIT(16)
+#define OUTPUT_BIT_SHIFT_EN				BIT(16)
+#define INPUT_BLOCK_MODE_MSK			(0x03 << 12)
+#define INPUT_BLOCK_MODE				(0x01 << 12)
+#define OUTPUT_BLOCK_MODE_MSK			(0x03 << 10)
+#define OUTPUT_BLOCK_MODE				(0x01 << 10)
+#define INPUT_BAM_MODE					(0x3 << 12)
+#define OUTPUT_BAM_MODE					(0x3 << 10)
+#define PACK_EN							(0x1 << 15)
+#define UNPACK_EN						(0x1 << 14)
+#define PACK_EN_MSK						(0x1 << 15)
+#define UNPACK_EN_MSK					(0x1 << 14)
+#define OUTPUT_SERVICE_MSK				(0x1 << 8)
+#define INPUT_SERVICE_MSK				(0x1 << 9)
+#define OUTPUT_SERVICE_DIS				(0x1 << 8)
+#define INPUT_SERVICE_DIS				(0x1 << 9)
+#define BLSP0_SPI_DEASSERT_WAIT_REG		0x0310
+#define QUP_DATA_AVAILABLE_FOR_READ		BIT(5)
+#define SPI_INPUT_BLOCK_SIZE			4
+#define SPI_OUTPUT_BLOCK_SIZE			4
+#define SPI_BITLEN_MSK					0x07
+#define MAX_COUNT_SIZE					0xffff
+
+struct qup_spi_priv {
+	phys_addr_t base;
+	struct clk clk;
+	u32 num_cs;
+	struct gpio_desc cs_gpios[SPI_NUM_CHIPSELECTS];
+	bool cs_high;
+	u32 core_state;
+};
+
+static int qup_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
+{
+	struct qup_spi_priv *priv = dev_get_priv(dev);
+
+	debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
+
+	if (cs >= SPI_NUM_CHIPSELECTS)
+		return -ENODEV;
+
+	if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
+		return -EINVAL;
+
+	if (priv->cs_high)
+		enable = !enable;
+
+	return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
+}
+
+/*
+ * Function to write data to OUTPUT FIFO
+ */
+static void qup_spi_write_byte(struct udevice *dev, unsigned char data)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	/* Wait for space in the FIFO */
+	while ((readl(priv->base + QUP_OPERATIONAL) & QUP_OP_OUT_FIFO_FULL))
+		udelay(1);
+
+	/* Write the byte of data */
+	writel(data, priv->base + QUP_OUTPUT_FIFO);
+}
+
+/*
+ * Function to read data from Input FIFO
+ */
+static unsigned char qup_spi_read_byte(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	/* Wait for Data in FIFO */
+	while (!(readl(priv->base + QUP_OPERATIONAL) & QUP_DATA_AVAILABLE_FOR_READ)) {
+		printf("Stuck at FIFO data wait\n");
+		udelay(1);
+	}
+
+	/* Read a byte of data */
+	return readl(priv->base + QUP_INPUT_FIFO) & 0xff;
+}
+
+/*
+ * Function to check wheather Input or Output FIFO
+ * has data to be serviced
+ */
+static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	unsigned int count = TIMEOUT_CNT;
+	unsigned int status_flag;
+	unsigned int val;
+
+	do {
+		val = readl(priv->base + reg_addr);
+		count--;
+		if (count == 0)
+			return -ETIMEDOUT;
+
+		status_flag = ((val & QUP_OP_OUT_SERVICE_FLAG) | (val & QUP_OP_IN_SERVICE_FLAG));
+	} while (!status_flag);
+
+	return 0;
+}
+
+/*
+ * Function to configure Input and Output enable/disable
+ */
+static void qup_spi_enable_io_config(struct udevice *dev, u32 write_cnt, u32 read_cnt)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+
+	if (write_cnt) {
+		clrsetbits_le32(priv->base + QUP_CONFIG,
+				QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
+	} else {
+		clrsetbits_le32(priv->base + QUP_CONFIG,
+				QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
+	}
+
+	if (read_cnt) {
+		clrsetbits_le32(priv->base + QUP_CONFIG,
+				QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
+	} else {
+		clrsetbits_le32(priv->base + QUP_CONFIG,
+				QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
+	}
+}
+
+static int check_bit_state(struct udevice *dev, u32 reg_addr, int bit_num, int val,
+						   int us_delay)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	unsigned int count = TIMEOUT_CNT;
+	unsigned int bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
+
+	while (bit_val != val) {
+		count--;
+		if (count == 0)
+			return -ETIMEDOUT;
+		udelay(us_delay);
+		bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
+	}
+
+	return 0;
+}
+
+/*
+ * Check whether QUPn State is valid
+ */
+static int check_qup_state_valid(struct udevice *dev)
+{
+	return check_bit_state(dev, QUP_STATE, QUP_STATE_VALID, 1, 1);
+}
+
+/*
+ * Configure QUPn Core state
+ */
+static int qup_spi_config_spi_state(struct udevice *dev, unsigned int state)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	u32 val;
+	int ret;
+
+	ret = check_qup_state_valid(dev);
+	if (ret != 0)
+		return ret;
+
+	switch (state) {
+	case SPI_RUN_STATE:
+		/* Set the state to RUN */
+		val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
+					| QUP_STATE_RUN);
+		writel(val, priv->base + QUP_STATE);
+		ret = check_qup_state_valid(dev);
+		if (ret != 0)
+			return ret;
+		priv->core_state = SPI_CORE_RUNNING;
+		break;
+	case SPI_RESET_STATE:
+		/* Set the state to RESET */
+		val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
+					| QUP_STATE_RESET);
+		writel(val, priv->base + QUP_STATE);
+		ret = check_qup_state_valid(dev);
+		if (ret != 0)
+			return ret;
+		priv->core_state = SPI_CORE_RESET;
+		break;
+	default:
+		printf("Unsupported QUP SPI state: %d\n", state);
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+/*
+ * Function to read bytes number of data from the Input FIFO
+ */
+static int __qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	u32 val;
+	unsigned int i;
+	unsigned int read_bytes = bytes;
+	unsigned int fifo_count;
+	int ret = 0;
+	int state_config;
+
+	/* Configure no of bytes to read */
+	state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+	if (state_config)
+		return state_config;
+
+	/* Configure input and output enable */
+	qup_spi_enable_io_config(dev, 0, read_bytes);
+
+	writel(bytes, priv->base + QUP_MX_INPUT_CNT);
+
+	state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
+	if (state_config)
+		return state_config;
+
+	while (read_bytes) {
+		ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
+		if (ret != 0)
+			goto out;
+
+		val = readl(priv->base + QUP_OPERATIONAL);
+		if (val & QUP_OP_IN_SERVICE_FLAG) {
+			/*
+			 * acknowledge to hw that software will
+			 * read input data
+			 */
+			val &= QUP_OP_IN_SERVICE_FLAG;
+			writel(val, priv->base + QUP_OPERATIONAL);
+
+			fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ?
+					SPI_INPUT_BLOCK_SIZE : read_bytes);
+
+			for (i = 0; i < fifo_count; i++) {
+				*data_buffer = qup_spi_read_byte(dev);
+				data_buffer++;
+				read_bytes--;
+			}
+		}
+	}
+
+out:
+	/*
+	 * Put the SPI Core back in the Reset State
+	 * to end the transfer
+	 */
+	(void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+
+	return ret;
+}
+
+static int qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
+{
+	int length, ret;
+
+	while (bytes) {
+		length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
+
+		ret = __qup_spi_blsp_spi_read(dev, data_buffer, length);
+		if (ret != 0)
+			return ret;
+
+		data_buffer += length;
+		bytes -= length;
+	}
+
+	return 0;
+}
+
+/*
+ * Function to write data to the Output FIFO
+ */
+static int __qup_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	u32 val;
+	unsigned int i;
+	unsigned int write_len = bytes;
+	unsigned int read_len = bytes;
+	unsigned int fifo_count;
+	int ret = 0;
+	int state_config;
+
+	state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+	if (state_config)
+		return state_config;
+
+	writel(bytes, priv->base + QUP_MX_OUTPUT_CNT);
+	writel(bytes, priv->base + QUP_MX_INPUT_CNT);
+	state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
+	if (state_config)
+		return state_config;
+
+	/* Configure input and output enable */
+	qup_spi_enable_io_config(dev, write_len, read_len);
+
+	/*
+	 * read_len considered to ensure that we read the dummy data for the
+	 * write we performed. This is needed to ensure with WR-RD transaction
+	 * to get the actual data on the subsequent read cycle that happens
+	 */
+	while (write_len || read_len) {
+		ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
+		if (ret != 0)
+			goto out;
+
+		val = readl(priv->base + QUP_OPERATIONAL);
+		if (val & QUP_OP_OUT_SERVICE_FLAG) {
+			/*
+			 * acknowledge to hw that software will write
+			 * expected output data
+			 */
+			val &= QUP_OP_OUT_SERVICE_FLAG;
+			writel(val, priv->base + QUP_OPERATIONAL);
+
+			if (write_len > SPI_OUTPUT_BLOCK_SIZE)
+				fifo_count = SPI_OUTPUT_BLOCK_SIZE;
+			else
+				fifo_count = write_len;
+
+			for (i = 0; i < fifo_count; i++) {
+				/* Write actual data to output FIFO */
+				qup_spi_write_byte(dev, *cmd_buffer);
+				cmd_buffer++;
+				write_len--;
+			}
+		}
+		if (val & QUP_OP_IN_SERVICE_FLAG) {
+			/*
+			 * acknowledge to hw that software
+			 * will read input data
+			 */
+			val &= QUP_OP_IN_SERVICE_FLAG;
+			writel(val, priv->base + QUP_OPERATIONAL);
+
+			if (read_len > SPI_INPUT_BLOCK_SIZE)
+				fifo_count = SPI_INPUT_BLOCK_SIZE;
+			else
+				fifo_count = read_len;
+
+			for (i = 0; i < fifo_count; i++) {
+				/* Read dummy data for the data written */
+				(void)qup_spi_read_byte(dev);
+
+				/* Decrement the write count after reading the
+				 * dummy data from the device. This is to make
+				 * sure we read dummy data before we write the
+				 * data to fifo
+				 */
+				read_len--;
+			}
+		}
+	}
+out:
+	/*
+	 * Put the SPI Core back in the Reset State
+	 * to end the transfer
+	 */
+	(void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+
+	return ret;
+}
+
+static int qup_spi_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
+{
+	int length, ret;
+
+	while (bytes) {
+		length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
+
+		ret = __qup_blsp_spi_write(dev, cmd_buffer, length);
+		if (ret != 0)
+			return ret;
+
+		cmd_buffer += length;
+		bytes -= length;
+	}
+
+	return 0;
+}
+
+static int qup_spi_set_speed(struct udevice *dev, uint speed)
+{
+	return 0;
+}
+
+static int qup_spi_set_mode(struct udevice *dev, uint mode)
+{
+	struct qup_spi_priv *priv = dev_get_priv(dev);
+	unsigned int clk_idle_state;
+	unsigned int input_first_mode;
+	u32 val;
+
+	switch (mode) {
+	case SPI_MODE_0:
+		clk_idle_state = 0;
+		input_first_mode = SPI_CONFIG_INPUT_FIRST;
+		break;
+	case SPI_MODE_1:
+		clk_idle_state = 0;
+		input_first_mode = 0;
+		break;
+	case SPI_MODE_2:
+		clk_idle_state = 1;
+		input_first_mode = SPI_CONFIG_INPUT_FIRST;
+		break;
+	case SPI_MODE_3:
+		clk_idle_state = 1;
+		input_first_mode = 0;
+		break;
+	default:
+		printf("Unsupported spi mode: %d\n", mode);
+		return -EINVAL;
+	}
+
+	if (mode & SPI_CS_HIGH)
+		priv->cs_high = true;
+	else
+		priv->cs_high = false;
+
+	val = readl(priv->base + SPI_CONFIG);
+	val |= input_first_mode;
+	writel(val, priv->base + SPI_CONFIG);
+
+	val = readl(priv->base + SPI_IO_CONTROL);
+	if (clk_idle_state)
+		val |= SPI_IO_C_CLK_IDLE_HIGH;
+	else
+		val &= ~SPI_IO_C_CLK_IDLE_HIGH;
+
+	writel(val, priv->base + SPI_IO_CONTROL);
+
+	return 0;
+}
+
+static void qup_spi_reset(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+
+	/* Driver may not be probed yet */
+	if (!priv)
+		return;
+
+	writel(0x1, priv->base + QUP_SW_RESET);
+	udelay(5);
+}
+
+static int qup_spi_hw_init(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct qup_spi_priv *priv = dev_get_priv(bus);
+	int ret;
+
+	/* QUPn module configuration */
+	qup_spi_reset(dev);
+
+	/* Set the QUPn state */
+	ret = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
+	if (ret)
+		return ret;
+
+	/*
+	 * Configure Mini core to SPI core with Input Output enabled,
+	 * SPI master, N = 8 bits
+	 */
+	clrsetbits_le32(priv->base + QUP_CONFIG, (QUP_CONFIG_MINI_CORE_MSK |
+						QUP_CONF_INPUT_MSK |
+						QUP_CONF_OUTPUT_MSK |
+						SPI_BIT_WORD_MSK),
+						(QUP_CONFIG_MINI_CORE_SPI |
+						QUP_CONF_INPUT_ENA |
+						QUP_CONF_OUTPUT_ENA |
+						SPI_8_BIT_WORD));
+
+	/*
+	 * Configure Input first SPI protocol,
+	 * SPI master mode and no loopback
+	 */
+	clrsetbits_le32(priv->base + SPI_CONFIG, (LOOP_BACK_MSK |
+						SLAVE_OPERATION_MSK),
+						(NO_LOOP_BACK |
+						SLAVE_OPERATION));
+
+	/*
+	 * Configure SPI IO Control Register
+	 * CLK_ALWAYS_ON = 0
+	 * MX_CS_MODE = 0
+	 * NO_TRI_STATE = 1
+	 */
+	writel((CLK_ALWAYS_ON | NO_TRI_STATE), priv->base + SPI_IO_CONTROL);
+
+	/*
+	 * Configure SPI IO Modes.
+	 * OUTPUT_BIT_SHIFT_EN = 1
+	 * INPUT_MODE = Block Mode
+	 * OUTPUT MODE = Block Mode
+	 */
+
+	clrsetbits_le32(priv->base + QUP_IO_M_MODES, (OUTPUT_BIT_SHIFT_MSK |
+				INPUT_BLOCK_MODE_MSK |
+				OUTPUT_BLOCK_MODE_MSK),
+				(OUTPUT_BIT_SHIFT_EN |
+				INPUT_BLOCK_MODE |
+				OUTPUT_BLOCK_MODE));
+
+	/* Disable Error mask */
+	writel(0, priv->base + SPI_ERROR_FLAGS_EN);
+	writel(0, priv->base + QUP_ERROR_FLAGS_EN);
+	writel(0, priv->base + BLSP0_SPI_DEASSERT_WAIT_REG);
+
+	return ret;
+}
+
+static int qup_spi_claim_bus(struct udevice *dev)
+{
+	int ret;
+
+	ret = qup_spi_hw_init(dev);
+	if (ret)
+		return -EIO;
+
+	return 0;
+}
+
+static int qup_spi_release_bus(struct udevice *dev)
+{
+	/* Reset the SPI hardware */
+	qup_spi_reset(dev);
+
+	return 0;
+}
+
+static int qup_spi_xfer(struct udevice *dev, unsigned int bitlen,
+						const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+	unsigned int len;
+	const u8 *txp = dout;
+	u8 *rxp = din;
+	int ret = 0;
+
+	if (bitlen & SPI_BITLEN_MSK) {
+		printf("Invalid bit length\n");
+		return -EINVAL;
+	}
+
+	len = bitlen >> 3;
+
+	if (flags & SPI_XFER_BEGIN) {
+		ret = qup_spi_hw_init(dev);
+		if (ret != 0)
+			return ret;
+
+		ret = qup_spi_set_cs(bus, slave_plat->cs, false);
+		if (ret != 0)
+			return ret;
+	}
+
+	if (dout != NULL) {
+		ret = qup_spi_blsp_spi_write(dev, txp, len);
+		if (ret != 0)
+			return ret;
+	}
+
+	if (din != NULL) {
+		ret = qup_spi_blsp_spi_read(dev, rxp, len);
+		if (ret != 0)
+			return ret;
+	}
+
+	if (flags & SPI_XFER_END) {
+		ret = qup_spi_set_cs(bus, slave_plat->cs, true);
+		if (ret != 0)
+			return ret;
+	}
+
+	return ret;
+}
+
+static int qup_spi_probe(struct udevice *dev)
+{
+	struct qup_spi_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = clk_get_by_index(dev, 0, &priv->clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret < 0)
+		return ret;
+
+	priv->num_cs = dev_read_u32_default(dev, "num-cs", 1);
+
+	ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
+					priv->num_cs, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret < 0) {
+		printf("Can't get %s cs gpios: %d\n", dev->name, ret);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct dm_spi_ops qup_spi_ops = {
+	.claim_bus	= qup_spi_claim_bus,
+	.release_bus	= qup_spi_release_bus,
+	.xfer		= qup_spi_xfer,
+	.set_speed	= qup_spi_set_speed,
+	.set_mode	= qup_spi_set_mode,
+	/*
+	 * cs_info is not needed, since we require all chip selects to be
+	 * in the device tree explicitly
+	 */
+};
+
+static const struct udevice_id qup_spi_ids[] = {
+	{ .compatible = "qcom,spi-qup-v1.1.1", },
+	{ .compatible = "qcom,spi-qup-v2.1.1", },
+	{ .compatible = "qcom,spi-qup-v2.2.1", },
+	{ }
+};
+
+U_BOOT_DRIVER(spi_qup) = {
+	.name	= "spi_qup",
+	.id	= UCLASS_SPI,
+	.of_match = qup_spi_ids,
+	.ops	= &qup_spi_ops,
+	.priv_auto_alloc_size	= sizeof(struct qup_spi_priv),
+	.probe	= qup_spi_probe,
+};
diff --git a/drivers/timer/ag101p_timer.c b/drivers/timer/ag101p_timer.c
index c011906b93..23ad5b2b67 100644
--- a/drivers/timer/ag101p_timer.c
+++ b/drivers/timer/ag101p_timer.c
@@ -62,14 +62,13 @@ struct atftmr_timer_platdata {
 	struct atftmr_timer_regs *regs;
 };
 
-static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
+static u64 atftmr_timer_get_count(struct udevice *dev)
 {
 	struct atftmr_timer_platdata *plat = dev->platdata;
 	struct atftmr_timer_regs *const regs = plat->regs;
 	u32 val;
 	val = readl(&regs->t3_counter);
-	*count = timer_conv_64(val);
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int atftmr_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c
index 6cb2923e0b..ccc164ee17 100644
--- a/drivers/timer/altera_timer.c
+++ b/drivers/timer/altera_timer.c
@@ -32,7 +32,7 @@ struct altera_timer_platdata {
 	struct altera_timer_regs *regs;
 };
 
-static int altera_timer_get_count(struct udevice *dev, u64 *count)
+static u64 altera_timer_get_count(struct udevice *dev)
 {
 	struct altera_timer_platdata *plat = dev->platdata;
 	struct altera_timer_regs *const regs = plat->regs;
@@ -44,9 +44,7 @@ static int altera_timer_get_count(struct udevice *dev, u64 *count)
 	/* Read timer value */
 	val = readl(&regs->snapl) & 0xffff;
 	val |= (readl(&regs->snaph) & 0xffff) << 16;
-	*count = timer_conv_64(~val);
-
-	return 0;
+	return timer_conv_64(~val);
 }
 
 static int altera_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/arc_timer.c b/drivers/timer/arc_timer.c
index 8c574ec5af..2dea9f40cb 100644
--- a/drivers/timer/arc_timer.c
+++ b/drivers/timer/arc_timer.c
@@ -26,7 +26,7 @@ struct arc_timer_priv {
 		uint timer_id;
 };
 
-static int arc_timer_get_count(struct udevice *dev, u64 *count)
+static u64 arc_timer_get_count(struct udevice *dev)
 {
 	u32 val = 0;
 	struct arc_timer_priv *priv = dev_get_priv(dev);
@@ -39,9 +39,7 @@ static int arc_timer_get_count(struct udevice *dev, u64 *count)
 		val = read_aux_reg(ARC_AUX_TIMER1_CNT);
 		break;
 	}
-	*count = timer_conv_64(val);
-
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int arc_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c
index e313249740..35369a4087 100644
--- a/drivers/timer/ast_timer.c
+++ b/drivers/timer/ast_timer.c
@@ -51,13 +51,11 @@ static int ast_timer_probe(struct udevice *dev)
 	return 0;
 }
 
-static int ast_timer_get_count(struct udevice *dev, u64 *count)
+static u64 ast_timer_get_count(struct udevice *dev)
 {
 	struct ast_timer_priv *priv = dev_get_priv(dev);
 
-	*count = AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
-
-	return 0;
+	return AST_TMC_RELOAD_VAL - readl(&priv->tmc->status);
 }
 
 static int ast_timer_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/timer/atcpit100_timer.c b/drivers/timer/atcpit100_timer.c
index 5d4ae68509..fcb8a45358 100644
--- a/drivers/timer/atcpit100_timer.c
+++ b/drivers/timer/atcpit100_timer.c
@@ -68,13 +68,12 @@ struct atcpit_timer_platdata {
 	u32 *regs;
 };
 
-static int atcpit_timer_get_count(struct udevice *dev, u64 *count)
+static u64 atcpit_timer_get_count(struct udevice *dev)
 {
 	struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
 	u32 val;
 	val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
-	*count = timer_conv_64(val);
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int atcpit_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c
index 843d670b5e..9f0ad1d703 100644
--- a/drivers/timer/atmel_pit_timer.c
+++ b/drivers/timer/atmel_pit_timer.c
@@ -25,15 +25,13 @@ struct atmel_pit_platdata {
 	struct atmel_pit_regs *regs;
 };
 
-static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+static u64 atmel_pit_get_count(struct udevice *dev)
 {
 	struct atmel_pit_platdata *plat = dev_get_platdata(dev);
 	struct atmel_pit_regs *const regs = plat->regs;
 	u32 val = readl(&regs->value_image);
 
-	*count = timer_conv_64(val);
-
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int atmel_pit_probe(struct udevice *dev)
diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c
index e6b6dfe376..bebb2c2e90 100644
--- a/drivers/timer/cadence-ttc.c
+++ b/drivers/timer/cadence-ttc.c
@@ -57,13 +57,11 @@ ulong timer_get_boot_us(void)
 }
 #endif
 
-static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
+static u64 cadence_ttc_get_count(struct udevice *dev)
 {
 	struct cadence_ttc_priv *priv = dev_get_priv(dev);
 
-	*count = readl(&priv->regs->counter_val1);
-
-	return 0;
+	return readl(&priv->regs->counter_val1);
 }
 
 static int cadence_ttc_probe(struct udevice *dev)
diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c
index 35271b20c8..68bc258131 100644
--- a/drivers/timer/dw-apb-timer.c
+++ b/drivers/timer/dw-apb-timer.c
@@ -25,7 +25,7 @@ struct dw_apb_timer_priv {
 	struct reset_ctl_bulk resets;
 };
 
-static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
+static u64 dw_apb_timer_get_count(struct udevice *dev)
 {
 	struct dw_apb_timer_priv *priv = dev_get_priv(dev);
 
@@ -34,9 +34,7 @@ static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
 	 * requires the count to be incrementing. Invert the
 	 * result.
 	 */
-	*count = timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
-
-	return 0;
+	return timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
 }
 
 static int dw_apb_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/mchp-pit64b-timer.c b/drivers/timer/mchp-pit64b-timer.c
index ead8c9b84a..ad962098b3 100644
--- a/drivers/timer/mchp-pit64b-timer.c
+++ b/drivers/timer/mchp-pit64b-timer.c
@@ -27,16 +27,14 @@ struct mchp_pit64b_priv {
 	void __iomem *base;
 };
 
-static int mchp_pit64b_get_count(struct udevice *dev, u64 *count)
+static u64 mchp_pit64b_get_count(struct udevice *dev)
 {
 	struct mchp_pit64b_priv *priv = dev_get_priv(dev);
 
 	u32 lsb = readl(priv->base + MCHP_PIT64B_TLSBR);
 	u32 msb = readl(priv->base + MCHP_PIT64B_TMSBR);
 
-	*count = ((u64)msb << 32) | lsb;
-
-	return 0;
+	return ((u64)msb << 32) | lsb;
 }
 
 static int mchp_pit64b_probe(struct udevice *dev)
diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c
index ad8bb28e8b..ba7704225a 100644
--- a/drivers/timer/mpc83xx_timer.c
+++ b/drivers/timer/mpc83xx_timer.c
@@ -187,7 +187,7 @@ void wait_ticks(ulong ticks)
 		WATCHDOG_RESET();
 }
 
-static int mpc83xx_timer_get_count(struct udevice *dev, u64 *count)
+static u64 mpc83xx_timer_get_count(struct udevice *dev)
 {
 	u32 tbu, tbl;
 
@@ -201,9 +201,7 @@ static int mpc83xx_timer_get_count(struct udevice *dev, u64 *count)
 		tbl = mftb();
 	} while (tbu != mftbu());
 
-	*count = (tbu * 0x10000ULL) + tbl;
-
-	return 0;
+	return (tbu * 0x10000ULL) + tbl;
 }
 
 static int mpc83xx_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
index 69ed521811..74e9ea34ff 100644
--- a/drivers/timer/mtk_timer.c
+++ b/drivers/timer/mtk_timer.c
@@ -27,14 +27,12 @@ struct mtk_timer_priv {
 	void __iomem *base;
 };
 
-static int mtk_timer_get_count(struct udevice *dev, u64 *count)
+static u64 mtk_timer_get_count(struct udevice *dev)
 {
 	struct mtk_timer_priv *priv = dev_get_priv(dev);
 	u32 val = readl(priv->base + MTK_GPT4_CNT);
 
-	*count = timer_conv_64(val);
-
-	return 0;
+	return timer_conv_64(val);
 }
 
 static int mtk_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/nomadik-mtu-timer.c b/drivers/timer/nomadik-mtu-timer.c
index 7ff921385a..d7f7ca4eff 100644
--- a/drivers/timer/nomadik-mtu-timer.c
+++ b/drivers/timer/nomadik-mtu-timer.c
@@ -54,14 +54,12 @@ struct nomadik_mtu_priv {
 	struct nomadik_mtu_timer_regs *timer;
 };
 
-static int nomadik_mtu_get_count(struct udevice *dev, u64 *count)
+static u64 nomadik_mtu_get_count(struct udevice *dev)
 {
 	struct nomadik_mtu_priv *priv = dev_get_priv(dev);
 
 	/* Decrementing counter: invert the value */
-	*count = timer_conv_64(~readl(&priv->timer->cv));
-
-	return 0;
+	return timer_conv_64(~readl(&priv->timer->cv));
 }
 
 static int nomadik_mtu_probe(struct udevice *dev)
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index cf3d27b96b..4eecb3e64d 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -48,13 +48,11 @@ struct omap_timer_priv {
 	struct omap_gptimer_regs *regs;
 };
 
-static int omap_timer_get_count(struct udevice *dev, u64 *count)
+static u64 omap_timer_get_count(struct udevice *dev)
 {
 	struct omap_timer_priv *priv = dev_get_priv(dev);
 
-	*count = timer_conv_64(readl(&priv->regs->tcrr));
-
-	return 0;
+	return timer_conv_64(readl(&priv->regs->tcrr));
 }
 
 static int omap_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c
index bea97159eb..bb0636a071 100644
--- a/drivers/timer/ostm_timer.c
+++ b/drivers/timer/ostm_timer.c
@@ -27,13 +27,11 @@ struct ostm_priv {
 	fdt_addr_t	regs;
 };
 
-static int ostm_get_count(struct udevice *dev, u64 *count)
+static u64 ostm_get_count(struct udevice *dev)
 {
 	struct ostm_priv *priv = dev_get_priv(dev);
 
-	*count = timer_conv_64(readl(priv->regs + OSTM_CNT));
-
-	return 0;
+	return timer_conv_64(readl(priv->regs + OSTM_CNT));
 }
 
 static int ostm_probe(struct udevice *dev)
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 449fcfcfd5..21ae184057 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,22 +16,19 @@
 #include <timer.h>
 #include <asm/csr.h>
 
-static int riscv_timer_get_count(struct udevice *dev, u64 *count)
+static u64 riscv_timer_get_count(struct udevice *dev)
 {
-	if (IS_ENABLED(CONFIG_64BIT)) {
-		*count = csr_read(CSR_TIME);
-	} else {
-		u32 hi, lo;
+	__maybe_unused u32 hi, lo;
 
-		do {
-			hi = csr_read(CSR_TIMEH);
-			lo = csr_read(CSR_TIME);
-		} while (hi != csr_read(CSR_TIMEH));
+	if (IS_ENABLED(CONFIG_64BIT))
+		return csr_read(CSR_TIME);
 
-		*count = ((u64)hi << 32) | lo;
-	}
+	do {
+		hi = csr_read(CSR_TIMEH);
+		lo = csr_read(CSR_TIME);
+	} while (hi != csr_read(CSR_TIMEH));
 
-	return 0;
+	return ((u64)hi << 32) | lo;
 }
 
 static int riscv_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
index 7a5a484252..53cdf09810 100644
--- a/drivers/timer/rockchip_timer.c
+++ b/drivers/timer/rockchip_timer.c
@@ -88,14 +88,13 @@ ulong timer_get_boot_us(void)
 }
 #endif
 
-static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
+static u64 rockchip_timer_get_count(struct udevice *dev)
 {
 	struct rockchip_timer_priv *priv = dev_get_priv(dev);
 	uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
 
 	/* timers are down-counting */
-	*count = ~0ull - cntr;
-	return 0;
+	return ~0ull - cntr;
 }
 
 static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c
index 6a503c2f15..135c0f38a4 100644
--- a/drivers/timer/sandbox_timer.c
+++ b/drivers/timer/sandbox_timer.c
@@ -29,11 +29,9 @@ unsigned long notrace timer_early_get_rate(void)
 	return SANDBOX_TIMER_RATE;
 }
 
-static notrace int sandbox_timer_get_count(struct udevice *dev, u64 *count)
+static notrace u64 sandbox_timer_get_count(struct udevice *dev)
 {
-	*count = timer_early_get_count();
-
-	return 0;
+	return timer_early_get_count();
 }
 
 static int sandbox_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/sti-timer.c b/drivers/timer/sti-timer.c
index ff42056abd..e6843ebb33 100644
--- a/drivers/timer/sti-timer.c
+++ b/drivers/timer/sti-timer.c
@@ -17,7 +17,7 @@ struct sti_timer_priv {
 	struct globaltimer *global_timer;
 };
 
-static int sti_timer_get_count(struct udevice *dev, u64 *count)
+static u64 sti_timer_get_count(struct udevice *dev)
 {
 	struct sti_timer_priv *priv = dev_get_priv(dev);
 	struct globaltimer *global_timer = priv->global_timer;
@@ -34,9 +34,7 @@ static int sti_timer_get_count(struct udevice *dev, u64 *count)
 			old = high;
 	}
 	timer = high;
-	*count = (u64)((timer << 32) | low);
-
-	return 0;
+	return (u64)((timer << 32) | low);
 }
 
 static int sti_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c
index c57fa3f557..f517d5e61f 100644
--- a/drivers/timer/stm32_timer.c
+++ b/drivers/timer/stm32_timer.c
@@ -52,14 +52,12 @@ struct stm32_timer_priv {
 	struct stm32_timer_regs *base;
 };
 
-static int stm32_timer_get_count(struct udevice *dev, u64 *count)
+static u64 stm32_timer_get_count(struct udevice *dev)
 {
 	struct stm32_timer_priv *priv = dev_get_priv(dev);
 	struct stm32_timer_regs *regs = priv->base;
 
-	*count = readl(&regs->cnt);
-
-	return 0;
+	return readl(&regs->cnt);
 }
 
 static int stm32_timer_probe(struct udevice *dev)
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index f8a092b8cb..62d0e860e8 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -34,7 +34,8 @@ int notrace timer_get_count(struct udevice *dev, u64 *count)
 	if (!ops->get_count)
 		return -ENOSYS;
 
-	return ops->get_count(dev, count);
+	*count = ops->get_count(dev);
+	return 0;
 }
 
 unsigned long notrace timer_get_rate(struct udevice *dev)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 93c959ff44..abc0a1da05 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -386,13 +386,11 @@ void __udelay(unsigned long usec)
 #endif
 }
 
-static int tsc_timer_get_count(struct udevice *dev, u64 *count)
+static u64 tsc_timer_get_count(struct udevice *dev)
 {
 	u64 now_tick = rdtsc();
 
-	*count = now_tick - gd->arch.tsc_base;
-
-	return 0;
+	return now_tick - gd->arch.tsc_base;
 }
 
 static void tsc_timer_ensure_setup(bool early)
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 64831a4223..a761e3d52f 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c
@@ -494,13 +494,13 @@ static int process_reset(struct udevice *dev)
 			continue;
 		}
 
-		log_warning("TPM ready after %ld ms\n", get_timer(start));
+		log_debug("TPM ready after %ld ms\n", get_timer(start));
 
 		return 0;
 	} while (get_timer(start) < TIMEOUT_INIT_MS);
 
-	log_warning("TPM failed to reset after %ld ms, status: %#x\n",
-		    get_timer(start), access);
+	log_err("TPM failed to reset after %ld ms, status: %#x\n",
+		get_timer(start), access);
 
 	return -EPERM;
 }
@@ -539,7 +539,7 @@ static int claim_locality(struct udevice *dev, int loc)
 		log_err("Failed to claim locality\n");
 		return -EPERM;
 	}
-	log_info("Claimed locality %d\n", loc);
+	log_debug("Claimed locality %d\n", loc);
 	priv->locality = loc;
 
 	return 0;
@@ -577,7 +577,7 @@ static int cr50_i2c_cleanup(struct udevice *dev)
 {
 	struct cr50_priv *priv = dev_get_priv(dev);
 
-	printf("%s: cleanup %d\n", __func__, priv->locality);
+	log_debug("cleanup %d\n", priv->locality);
 	if (priv->locality != -1)
 		release_locality(dev, 1);