diff options
| author | Joakim Tjernlund <joakim.tjernlund@infinera.com> | 2019-11-27 19:35:10 +0100 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2019-12-23 14:07:55 +0530 |
| commit | 2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee (patch) | |
| tree | 251f9fa102648ac6c3167aa1a0694cbdd4a6b97c /drivers | |
| parent | 71094b72d7113cbb2c566eac43fc122a18e5c6f9 (diff) | |
| download | u-boot-2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee.tar.gz u-boot-2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee.tar.xz u-boot-2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee.zip | |
mpc85xx: ddr: Always start DDR RAM in Self Refresh mode
Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index a9b085db8c..952b296dd8 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -370,6 +370,8 @@ step2: debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); #endif /* part 1 of the workaound */ + /* Always start in self-refresh, clear after MEM_EN */ + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); /* * 500 painful micro-seconds must elapse between @@ -382,8 +384,6 @@ step2: #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { - /* enter self-refresh */ - setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); /* do board specific memory setup */ board_mem_sleep_setup(); temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); @@ -395,6 +395,10 @@ step2: out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("sync;isync"); + /* Exit self-refresh after DDR conf as some ddr memories can fail. */ + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); + asm volatile("sync;isync"); + total_gb_size_per_controller = 0; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (!(regs->cs[i].config & 0x80000000)) @@ -544,9 +548,4 @@ step2: clrbits_be32(&ddr->sdram_cfg, 0x2); } #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ -#ifdef CONFIG_DEEP_SLEEP - if (is_warm_boot()) - /* exit self-refresh */ - clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); -#endif } |