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| author | Joel Stanley <joel@jms.id.au> | 2019-06-06 17:08:45 +0930 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-06-20 10:57:08 -0400 |
| commit | 894e235f145b4f397a474f22c7c604ae925eb114 (patch) | |
| tree | 95cd9dd0502f2cad2ee496cee8cd1cf46798bd30 /drivers/watchdog | |
| parent | f2f83b2fd0b233ca971dfa5f4ddf8cd8a0cf33e3 (diff) | |
| download | u-boot-894e235f145b4f397a474f22c7c604ae925eb114.tar.gz u-boot-894e235f145b4f397a474f22c7c604ae925eb114.tar.xz u-boot-894e235f145b4f397a474f22c7c604ae925eb114.zip | |
aspeed/watchdog: Correct timeout value
The driver was using milliseconds and programming it into a register
which takes ticks of the watchdog clock, which runs at 1MHz. This meant
we were off by 1000 with the desired value.
When 06985289d452 ("watchdog: Implement generic watchdog_reset()
version") was added the aspeed board would leave the watchdog running,
causing it to bite before u-boot was done.
Discovered by booting in qemu:
$ qemu-system-arm -M ast2500-evb -drive file=test.img,format=raw,if=mtd -nographic -no-reboot -d cpu_reset
U-Boot 2019.07-rc3-00091-g2253e40caef5 (Jun 06 2019 - 16:53:23 +0930)
Model: Aspeed BMC
DRAM: 496 MiB
WDT: Started with servicing (60s timeout)
MMC:
In: serial@1e784000
Out: serial@1e784000
Err: serial@1e784000
Watchdog timer expired.
Fixes: 06985289d452 ("watchdog: Implement generic watchdog_reset() version")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'drivers/watchdog')
| -rw-r--r-- | drivers/watchdog/ast_wdt.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c index 523484b1ff..d344d54aee 100644 --- a/drivers/watchdog/ast_wdt.c +++ b/drivers/watchdog/ast_wdt.c @@ -23,6 +23,12 @@ static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags) ulong driver_data = dev_get_driver_data(dev); u32 reset_mode = ast_reset_mode_from_flags(flags); + /* 32 bits at 1MHz is 4294967ms */ + timeout = min_t(u64, timeout, 4294967); + + /* WDT counts in ticks of 1MHz clock. 1ms / 1e3 * 1e6 */ + timeout *= 1000; + clrsetbits_le32(&priv->regs->ctrl, WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT, reset_mode << WDT_CTRL_RESET_MODE_SHIFT); |