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| author | Simon Glass <sjg@chromium.org> | 2015-04-14 21:03:44 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-05-13 09:24:12 -0700 |
| commit | dedc44b466ba24bd4f38840a79067d806d37d709 (patch) | |
| tree | f371ffada3e1b602c30433aff3af0baaead170f9 /drivers/video/tegra124/sor.h | |
| parent | 531eaedc7a397b34979c6d35e5de7b78d2dddfde (diff) | |
| download | u-boot-dedc44b466ba24bd4f38840a79067d806d37d709.tar.gz u-boot-dedc44b466ba24bd4f38840a79067d806d37d709.tar.xz u-boot-dedc44b466ba24bd4f38840a79067d806d37d709.zip | |
tegra124: video: Add full link training for eDP
Add full link training as a fallback in case the fast link training
fails.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'drivers/video/tegra124/sor.h')
| -rw-r--r-- | drivers/video/tegra124/sor.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/video/tegra124/sor.h b/drivers/video/tegra124/sor.h index 7f1255c2b5..dc8fd03d80 100644 --- a/drivers/video/tegra124/sor.h +++ b/drivers/video/tegra124/sor.h @@ -848,6 +848,7 @@ struct tegra_dp_link_config { u32 bits_per_pixel; int alt_scramber_reset_cap; /* true for eDP */ int only_enhanced_framing; /* enhanced_frame_en ignored */ + int frame_in_ms; /* Actual configuration */ u8 link_bw; @@ -868,6 +869,8 @@ struct tegra_dp_link_config { u32 drive_current; u32 preemphasis; u32 postcursor; + u8 aux_rd_interval; + u8 tps3_supported; }; struct tegra_dc_sor_data { @@ -896,9 +899,24 @@ void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, const struct tegra_dp_link_config *link_cfg); void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor, const struct tegra_dp_link_config *link_cfg); +int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *link_cfg); +int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor, + const struct tegra_dp_link_config *cfg); +void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); +void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, + u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported); int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor, const struct tegra_dp_link_config *link_cfg, const struct display_timing *timing); +int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor); + +void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl, + int *dc_reg_ctx); +int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl); +void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl, + int *dc_reg_ctx); + int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp); #endif |