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| author | Priit Laes <priit.laes@paf.com> | 2018-12-19 15:06:08 +0200 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2019-02-15 16:28:58 +0100 |
| commit | 361604d658695966ba985f544800ecc7563caf41 (patch) | |
| tree | e7256b0fb28da5b348e1c7262ca8062858f8e84c /drivers/video/sunxi/sunxi_display.c | |
| parent | 63f7e3fca391a50a499fed828fe16325fdee45f3 (diff) | |
| download | u-boot-361604d658695966ba985f544800ecc7563caf41.tar.gz u-boot-361604d658695966ba985f544800ecc7563caf41.tar.xz u-boot-361604d658695966ba985f544800ecc7563caf41.zip | |
sunxi: display: Move DDC PLL setup to HDMI init
Move PLL initialization code to single place so
we won't call it every time we query for EDID data.
Signed-off-by: Priit Laes <priit.laes@paf.com>
Diffstat (limited to 'drivers/video/sunxi/sunxi_display.c')
| -rw-r--r-- | drivers/video/sunxi/sunxi_display.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 6dd9bec351..0362071f72 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -113,6 +113,13 @@ static int sunxi_hdmi_hpd_detect(int hpd_delay) writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl); writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0); + /* Enable PLLs for eventual DDC */ + writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE, + &hdmi->pad_ctrl1); + writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15), + &hdmi->pll_ctrl); + writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); + while (timer_get_us() < tmo) { if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT) return 1; @@ -215,13 +222,6 @@ static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; int i, r, ext_blocks = 0; - /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */ - writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE, - &hdmi->pad_ctrl1); - writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15), - &hdmi->pll_ctrl); - writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0); - /* Reset i2c controller */ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); writel(SUNXI_HMDI_DDC_CTRL_ENABLE | |