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| author | Marek Vasut <marex@denx.de> | 2020-04-22 13:18:14 +0200 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-05-14 09:02:12 +0200 |
| commit | 2d68365da17b7dc45543daaa9c5010c11332ba09 (patch) | |
| tree | 62db4764741b0e16415bf1bc12acbdea7f8aba24 /drivers/usb/cdns3 | |
| parent | a8c97f4a00fb5a9a31970351fce4355d37d19c7d (diff) | |
| download | u-boot-2d68365da17b7dc45543daaa9c5010c11332ba09.tar.gz u-boot-2d68365da17b7dc45543daaa9c5010c11332ba09.tar.xz u-boot-2d68365da17b7dc45543daaa9c5010c11332ba09.zip | |
ARM: stm32: Implement DDR3 coding on DHCOR SoM
The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'drivers/usb/cdns3')
0 files changed, 0 insertions, 0 deletions