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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-12 18:09:47 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-12 18:09:47 +0100 |
| commit | 034698329067f74b66a457aaf8924f7b054996eb (patch) | |
| tree | 7e2e1bd8a829e434d90983a5e9699040d196e6db /drivers/tsec.h | |
| parent | d8169c9f3ba04f5e470008c59afa3161ce683524 (diff) | |
| download | u-boot-034698329067f74b66a457aaf8924f7b054996eb.tar.gz u-boot-034698329067f74b66a457aaf8924f7b054996eb.tar.xz u-boot-034698329067f74b66a457aaf8924f7b054996eb.zip | |
Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode
Patch by Andy Fleming, 14 Jun 2005
Diffstat (limited to 'drivers/tsec.h')
| -rw-r--r-- | drivers/tsec.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/tsec.h b/drivers/tsec.h index e3bbff03bf..e92b53ad6b 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -124,7 +124,7 @@ /* Cicada 8204 Extended PHY Control Register 1 */ #define MIIM_CIS8204_EPHY_CON 0x17 #define MIIM_CIS8204_EPHYCON_INIT 0x0006 -#define MIIM_CIS8204_EPHYCON_RGMII 0x1000 +#define MIIM_CIS8204_EPHYCON_RGMII 0x1100 /* Cicada 8204 Serial LED Control Register */ #define MIIM_CIS8204_SLED_CON 0x1b |