Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2020.10

Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default

ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform

Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board

mmc:
- minor GD pointer removal

net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver

spi:
- Cleanup global macros for xilinx spi drivers

firmware:
- Add support for pmufw reloading

fpga:
- Improve error status reporting

common:
- Remove 4kB addition space for FDT allocation

3 files changed, 6 insertions, 12 deletions

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 05768eef72..348630faf3 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -76,9 +76,7 @@
 				SPICR_SPE)
 #define XILSPI_SPICR_DFLT_OFF	(SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
 
-#ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL	GENMASK(7, 0)
-#endif
+#define XILINX_SPI_IDLE_VAL	GENMASK(7, 0)
 
 #define XILINX_SPISR_TIMEOUT	10000 /* in milliseconds */
 
@@ -176,7 +174,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
 
 	while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
 	       i < priv->fifo_depth) {
-		d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+		d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
 		debug("spi_xfer: tx:%x ", d);
 		/* write out and wait for processing (receive data) */
 		writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index db473da6ea..3f39ef05f2 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -47,9 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_CR_SS_SHIFT		10	/* Slave select shift */
 
 #define ZYNQ_QSPI_FIFO_DEPTH		63
-#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
-#define CONFIG_SYS_ZYNQ_QSPI_WAIT	CONFIG_SYS_HZ/100	/* 10 ms */
-#endif
+#define ZYNQ_QSPI_WAIT			(CONFIG_SYS_HZ / 100)	/* 10 ms */
 
 /* zynq qspi register set */
 struct zynq_qspi_regs {
@@ -350,7 +348,7 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
 	do {
 		status = readl(&regs->isr);
 	} while ((status == 0) &&
-		(get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
+		(get_timer(timeout) < ZYNQ_QSPI_WAIT));
 
 	if (status == 0) {
 		printf("zynq_qspi_irq_poll: Timeout!\n");
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 3e66b34ebb..78ffd3e2fe 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -36,9 +36,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_SPI_CR_SS_SHIFT		10	/* Slave select shift */
 
 #define ZYNQ_SPI_FIFO_DEPTH		128
-#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
-#define CONFIG_SYS_ZYNQ_SPI_WAIT	(CONFIG_SYS_HZ/100)	/* 10 ms */
-#endif
+#define ZYNQ_SPI_WAIT			(CONFIG_SYS_HZ / 100)	/* 10 ms */
 
 /* zynq spi register set */
 struct zynq_spi_regs {
@@ -251,7 +249,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		ts = get_timer(0);
 		status = readl(&regs->isr);
 		while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
-			if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
+			if (get_timer(ts) > ZYNQ_SPI_WAIT) {
 				printf("spi_xfer: Timeout! TX FIFO not full\n");
 				return -1;
 			}