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author | David Wu <david.wu@rock-chips.com> | 2019-04-16 21:50:55 +0800 |
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committer | Kever Yang <kever.yang@rock-chips.com> | 2019-05-08 17:34:12 +0800 |
commit | 54e75702c48a9757e82cbe71176c0b5ddcf6a092 (patch) | |
tree | 5ba9d182d9b7e06c56f1e2c326551760c7825060 /drivers/pinctrl/rockchip/pinctrl-rk3128.c | |
parent | 8541beb86daf3ce7e4be9ca67859aab3dd0daefb (diff) | |
download | u-boot-54e75702c48a9757e82cbe71176c0b5ddcf6a092.tar.gz u-boot-54e75702c48a9757e82cbe71176c0b5ddcf6a092.tar.xz u-boot-54e75702c48a9757e82cbe71176c0b5ddcf6a092.zip |
pinctrl: rockchip: Split the common set_mux() into per Soc
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/pinctrl/rockchip/pinctrl-rk3128.c')
-rw-r--r-- | drivers/pinctrl/rockchip/pinctrl-rk3128.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index 43a6c173a0..de203334c7 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -98,6 +98,42 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = { }, }; +static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3128_PULL_OFFSET 0x118 #define RK3128_PULL_PINS_PER_REG 16 #define RK3128_PULL_BANK_STRIDE 8 @@ -133,6 +169,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), .iomux_routes = rk3128_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), + .set_mux = rk3128_set_mux, .pull_calc_reg = rk3128_calc_pull_reg_and_bit, }; |