Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>

3 files changed, 209 insertions, 4 deletions

diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index c5cf188f05..e19d7777dc 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -11,12 +11,14 @@
 #include "fm.h"
 #include <fsl_qe.h>		/* For struct qe_firmware */
 
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
-#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
 #include <spi_flash.h>
-#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
 #include <mmc.h>
+#include <environment.h>
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
 #endif
 
 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
@@ -347,6 +349,100 @@ static void fm_init_qmi(struct fm_qmi_common *qmi)
 }
 
 /* Init common part of FM, index is fm num# like fm as above */
+#ifdef CONFIG_TFABOOT
+int fm_init_common(int index, struct ccsr_fman *reg)
+{
+	int rc;
+	void *addr = NULL;
+	enum boot_src src = get_boot_src();
+
+	if (src == BOOT_SOURCE_IFC_NOR) {
+		addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
+				CONFIG_SYS_FSL_IFC_BASE);
+	} else if (src == BOOT_SOURCE_IFC_NAND) {
+		size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
+
+		addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+
+		rc = nand_read(get_nand_dev_by_index(0),
+			       (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+			       &fw_length, (u_char *)addr);
+		if (rc == -EUCLEAN) {
+			printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
+			       CONFIG_SYS_FMAN_FW_ADDR, rc);
+		}
+	} else if (src == BOOT_SOURCE_QSPI_NOR) {
+		struct spi_flash *ucode_flash;
+
+		addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+		int ret = 0;
+
+#ifdef CONFIG_DM_SPI_FLASH
+		struct udevice *new;
+
+		/* speed and mode will be read from DT */
+		ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
+					     CONFIG_ENV_SPI_CS, 0, 0, &new);
+
+		ucode_flash = dev_get_uclass_priv(new);
+#else
+		ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+					      CONFIG_ENV_SPI_CS,
+					      CONFIG_ENV_SPI_MAX_HZ,
+					      CONFIG_ENV_SPI_MODE);
+#endif
+		if (!ucode_flash) {
+			printf("SF: probe for ucode failed\n");
+		} else {
+			ret = spi_flash_read(ucode_flash,
+					     CONFIG_SYS_FMAN_FW_ADDR +
+					     CONFIG_SYS_FSL_QSPI_BASE,
+					     CONFIG_SYS_QE_FMAN_FW_LENGTH,
+					     addr);
+			if (ret)
+				printf("SF: read for ucode failed\n");
+			spi_flash_free(ucode_flash);
+		}
+	} else if (src == BOOT_SOURCE_SD_MMC) {
+		int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+		addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+		u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+		u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
+		struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+		if (!mmc) {
+			printf("\nMMC cannot find device for ucode\n");
+		} else {
+			printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
+			       dev, blk, cnt);
+			mmc_init(mmc);
+			(void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
+						addr);
+		}
+	} else {
+		addr = NULL;
+	}
+
+	/* Upload the Fman microcode if it's present */
+	rc = fman_upload_firmware(index, &reg->fm_imem, addr);
+	if (rc)
+		return rc;
+	env_set_addr("fman_ucode", addr);
+
+	fm_init_muram(index, &reg->muram);
+	fm_init_qmi(&reg->fm_qmi_common);
+	fm_init_fpm(&reg->fm_fpm);
+
+	/* clear DMA status */
+	setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
+
+	/* set DMA mode */
+	setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
+
+	return fm_init_bmi(index, &reg->fm_bmi_common);
+}
+#else
 int fm_init_common(int index, struct ccsr_fman *reg)
 {
 	int rc;
@@ -429,3 +525,4 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 
 	return fm_init_bmi(index, &reg->fm_bmi_common);
 }
+#endif
diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile
index 477ee4faed..1d85b2cfa8 100644
--- a/drivers/net/ldpaa_eth/Makefile
+++ b/drivers/net/ldpaa_eth/Makefile
@@ -1,8 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+
-#
+# Copyright 2015-2018 NXP
 # Copyright 2014 Freescale Semiconductor, Inc.
 
 obj-y += ldpaa_wriop.o
 obj-y += ldpaa_eth.o
 obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o
 obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o
+obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o
diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c
new file mode 100644
index 0000000000..7dd46c04f6
--- /dev/null
+++ b/drivers/net/ldpaa_eth/lx2160a.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+#include <common.h>
+#include <phy.h>
+#include <fsl-mc/ldpaa_wriop.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+
+u32 dpmac_to_devdisr[] = {
+	[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
+	[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
+	[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
+	[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
+	[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
+	[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
+	[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
+	[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
+	[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
+	[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
+	[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
+	[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
+	[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
+	[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
+	[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
+	[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
+	[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
+	[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
+};
+
+static int is_device_disabled(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 devdisr2 = in_le32(&gur->devdisr2);
+
+	return dpmac_to_devdisr[dpmac_id] & devdisr2;
+}
+
+void wriop_dpmac_disable(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+void wriop_dpmac_enable(int dpmac_id)
+{
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
+}
+
+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
+{
+	enum srds_prtcl;
+
+	if (is_device_disabled(dpmac_id + 1))
+		return PHY_INTERFACE_MODE_NONE;
+
+	if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
+		return PHY_INTERFACE_MODE_SGMII;
+
+	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
+		return PHY_INTERFACE_MODE_XGMII;
+
+	if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
+		return PHY_INTERFACE_MODE_25G_AUI;
+
+	if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
+		return PHY_INTERFACE_MODE_XLAUI;
+
+	if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
+		return PHY_INTERFACE_MODE_CAUI2;
+
+	if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
+		return PHY_INTERFACE_MODE_CAUI4;
+
+	return PHY_INTERFACE_MODE_NONE;
+}
+
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+void fsl_rgmii_init(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 ec;
+
+#ifdef CONFIG_SYS_FSL_EC1
+	ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
+		& FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
+	ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
+
+	if (!ec)
+		wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
+#endif
+
+#ifdef CONFIG_SYS_FSL_EC2
+	ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
+		& FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
+	ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
+
+	if (!ec)
+		wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
+#endif
+}
+#endif