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| author | Michal Simek <michal.simek@xilinx.com> | 2018-08-22 16:18:34 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-10-16 16:53:24 +0200 |
| commit | 3dc80934f4651a3ef243a393be04b1f7f71daf24 (patch) | |
| tree | 47991cc6058205842cc8da5722917c72a7af1e3e /drivers/net/zynq_gem.c | |
| parent | ec48b6c991f400c8583ac2f875d65a8539f0b437 (diff) | |
| download | u-boot-3dc80934f4651a3ef243a393be04b1f7f71daf24.tar.gz u-boot-3dc80934f4651a3ef243a393be04b1f7f71daf24.tar.xz u-boot-3dc80934f4651a3ef243a393be04b1f7f71daf24.zip | |
net: gem: Do not setup any clock for Xilinx SoC Versal
Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/net/zynq_gem.c')
| -rw-r--r-- | drivers/net/zynq_gem.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index e22d048e8f..bc33126536 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -461,6 +461,7 @@ static int zynq_gem_init(struct udevice *dev) break; } +#if !defined(CONFIG_ARCH_VERSAL) ret = clk_set_rate(&priv->clk, clk_rate); if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { dev_err(dev, "failed to set tx clock rate\n"); @@ -472,6 +473,9 @@ static int zynq_gem_init(struct udevice *dev) dev_err(dev, "failed to enable tx clock\n"); return ret; } +#else + debug("requested clk_rate %ld\n", clk_rate); +#endif setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); |