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| author | Horatiu Vultur <horatiu.vultur@microchip.com> | 2021-03-10 09:31:38 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2021-04-22 02:34:45 +0200 |
| commit | 6b59304602f2f954f22b96ec33e021591d1dc16f (patch) | |
| tree | ffd4179e18867c25764682c4b132442e7d8800f8 /drivers/net/mscc_eswitch/jr2_switch.c | |
| parent | 842d049be23976ebcbb2522fa8d752d3aae8631a (diff) | |
| download | u-boot-6b59304602f2f954f22b96ec33e021591d1dc16f.tar.gz u-boot-6b59304602f2f954f22b96ec33e021591d1dc16f.tar.xz u-boot-6b59304602f2f954f22b96ec33e021591d1dc16f.zip | |
net: jr2: Reset switch
Make sure to reset the switch core at probe time.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Diffstat (limited to 'drivers/net/mscc_eswitch/jr2_switch.c')
| -rw-r--r-- | drivers/net/mscc_eswitch/jr2_switch.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c index 128d7f21ce..9ba6ccc1bb 100644 --- a/drivers/net/mscc_eswitch/jr2_switch.c +++ b/drivers/net/mscc_eswitch/jr2_switch.c @@ -235,7 +235,7 @@ static const char * const regs_names[] = { "port36", "port37", "port38", "port39", "port40", "port41", "port42", "port43", "port44", "port45", "port46", "port47", "ana_ac", "ana_cl", "ana_l2", "asm", "hsio", "lrn", - "qfwd", "qs", "qsys", "rew", + "qfwd", "qs", "qsys", "rew", "gcb", "icpu", }; #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1 @@ -252,6 +252,8 @@ enum jr2_ctrl_regs { QS, QSYS, REW, + GCB, + ICPU, }; #define JR2_MIIM_BUS_COUNT 3 @@ -850,6 +852,7 @@ static int jr2_probe(struct udevice *dev) struct mii_dev *bus; struct ofnode_phandle_args phandle; struct phy_device *phy; + u32 val; if (!priv) return -EINVAL; @@ -865,6 +868,17 @@ static int jr2_probe(struct udevice *dev) } } + val = readl(priv->regs[ICPU] + ICPU_RESET); + val |= ICPU_RESET_CORE_RST_PROTECT; + writel(val, priv->regs[ICPU] + ICPU_RESET); + + val = readl(priv->regs[GCB] + PERF_SOFT_RST); + val |= PERF_SOFT_RST_SOFT_SWC_RST; + writel(val, priv->regs[GCB] + PERF_SOFT_RST); + + while (readl(priv->regs[GCB] + PERF_SOFT_RST) & PERF_SOFT_RST_SOFT_SWC_RST) + ; + /* Initialize miim buses */ memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * JR2_MIIM_BUS_COUNT); |