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| author | Alex Marginean <alexandru.marginean@nxp.com> | 2019-07-03 12:11:42 +0300 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2019-07-25 13:13:30 -0500 |
| commit | e4aafd5c207002f54b1dfd99b0b9e397c68dbe28 (patch) | |
| tree | cd4d3766e413da96a733bf603948bf590cf8903b /drivers/net/fsl_enetc.h | |
| parent | 1d99534beffea9b8e54a2cf31776cff68c4fc676 (diff) | |
| download | u-boot-e4aafd5c207002f54b1dfd99b0b9e397c68dbe28.tar.gz u-boot-e4aafd5c207002f54b1dfd99b0b9e397c68dbe28.tar.xz u-boot-e4aafd5c207002f54b1dfd99b0b9e397c68dbe28.zip | |
drivers: net: apply serdes configuration for ENETC Ethernet interfaces
Ethernet interfaces using serial protocols go through the serdes block
integrated in the SoC. This is accessed over dedicated internal MDIOs
which are part of the Ethernet PCI functions. Set up serdes at _start,
along with other protocol specific port/MAC configuration.
MDIO code is shared with enetc_mdio, read/write functions are exported
from fsl_enetc_mdio for this reason.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net/fsl_enetc.h')
| -rw-r--r-- | drivers/net/fsl_enetc.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index fbb9dfa15e..7ac7c1fefe 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -61,6 +61,8 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PSIPMMR 0x0018 #define ENETC_PSIPMAR0 0x0100 #define ENETC_PSIPMAR1 0x0104 +#define ENETC_PCAPR0 0x0900 +#define ENETC_PCAPRO_MDIO BIT(11) #define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10) #define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff) #define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16) @@ -70,6 +72,11 @@ enum enetc_bdr_type {TX, RX}; #define ENETC_PM_CC_RX_TX_EN 0x8813 #define ENETC_PM_MAXFRM 0x8014 #define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN +#define ENETC_PM_IMDIO_BASE 0x8030 +#define ENETC_PM_IF_MODE 0x8300 +#define ENETC_PM_IF_MODE_RG BIT(2) +#define ENETC_PM_IF_MODE_AN_ENA BIT(15) +#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0) /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */ #define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER @@ -146,6 +153,7 @@ struct enetc_priv { struct bd_ring rx_bdr; int if_type; + struct mii_dev imdio; }; /* register accessors */ @@ -168,6 +176,27 @@ struct enetc_priv { #define enetc_bdr_write(priv, t, n, off, val) \ enetc_write(priv, ENETC_BDR(t, n, off), val) +/* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */ +#define ENETC_PCS_PHY_ADDR 0 + +/* PCS registers */ +#define ENETC_PCS_CR 0x00 +#define ENETC_PCS_CR_RESET_AN 0x1200 +#define ENETC_PCS_CR_DEF_VAL 0x0140 +#define ENETC_PCS_CR_LANE_RESET 0x8000 +#define ENETC_PCS_DEV_ABILITY 0x04 +#define ENETC_PCS_DEV_ABILITY_SGMII 0x4001 +#define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001 +#define ENETC_PCS_LINK_TIMER1 0x12 +#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0 +#define ENETC_PCS_LINK_TIMER2 0x13 +#define ENETC_PCS_LINK_TIMER2_VAL 0x0003 +#define ENETC_PCS_IF_MODE 0x14 +#define ENETC_PCS_IF_MODE_SGMII_AN 0x0003 + +/* PCS replicator block for USXGMII */ +#define ENETC_PCS_DEVAD_REPL 0x1f + /* ENETC external MDIO registers */ #define ENETC_MDIO_BASE 0x1c00 #define ENETC_MDIO_CFG 0x00 @@ -186,4 +215,13 @@ struct enetc_mdio_priv { void *regs_base; }; +/* + * these functions are implemented by ENETC_MDIO and are re-used by ENETC driver + * to drive serdes / internal SoC PHYs + */ +int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad, + int reg); +int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad, + int reg, u16 val); + #endif /* _ENETC_H */ |