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authorMarek Vasut <marex@denx.de>2020-03-23 02:03:50 +0100
committermarex <marex@desktop.lan>2020-05-01 12:35:21 +0200
commit83858d87954627af7a576ccc7c93034b055faa7b (patch)
treef38086972a3d3c5070d173b36c9c5fbef69df5c7 /drivers/net/dwc_eth_qos.c
parent4332d8061785b697ae7bdf3945adb55ba4da696b (diff)
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net: dwc_eth_qos: Correctly wrap around TX descriptor tail pointer
This code programs the next descriptor in the TX descriptor ring into the hardware as the last valid TX descriptor. The problem is that if the currenty descriptor is the last one in the array, the code will not wrap around correctly and use TX descriptor 0 again, but instead will use TX descriptor at address right past the TX descriptor ring, which is the first descriptor in the RX ring. Fix this by adding the necessary wrap-around. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/net/dwc_eth_qos.c')
-rw-r--r--drivers/net/dwc_eth_qos.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 4f24520691..e2fb690a1c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1419,7 +1419,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length)
tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
eqos->config->ops->eqos_flush_desc(tx_desc);
- writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
+ writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])),
+ &eqos->dma_regs->ch0_txdesc_tail_pointer);
for (i = 0; i < 1000000; i++) {
eqos->config->ops->eqos_inval_desc(tx_desc);