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| author | Michal Simek <michal.simek@xilinx.com> | 2021-02-09 15:28:15 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-02-23 14:56:59 +0100 |
| commit | 9b7aac75365b68bae2e8f7cf074ba95638d31882 (patch) | |
| tree | 9d2ee4b001275fe6a2191ead6ec3913e033a783d /drivers/hwspinlock/hwspinlock-uclass.c | |
| parent | 3aba25bc382beeb8a92b46d23fd1db47dfcb1121 (diff) | |
| download | u-boot-9b7aac75365b68bae2e8f7cf074ba95638d31882.tar.gz u-boot-9b7aac75365b68bae2e8f7cf074ba95638d31882.tar.xz u-boot-9b7aac75365b68bae2e8f7cf074ba95638d31882.zip | |
clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/hwspinlock/hwspinlock-uclass.c')
0 files changed, 0 insertions, 0 deletions