diff options
author | Patrice Chotard <patrice.chotard@st.com> | 2017-12-12 09:49:40 +0100 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2018-01-10 08:05:46 -0500 |
commit | c8f787760ede974ec24407cc66966571384db606 (patch) | |
tree | 7f2602a0b622703e73e9a23b69efdf575bc97396 /drivers/gpio/stm32_gpio.c | |
parent | 4a56fd484a2e4a02ab372d299d0231002035f3ff (diff) | |
download | u-boot-c8f787760ede974ec24407cc66966571384db606.tar.gz u-boot-c8f787760ede974ec24407cc66966571384db606.tar.xz u-boot-c8f787760ede974ec24407cc66966571384db606.zip |
board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driver
Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers
instead of board GPIO initialization.
Remove stm32_gpio.c which is no more used and migrate
structs stm32_gpio_regs and stm32_gpio_priv into
arch-stm32f4/gpio.h to not break compilation.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'drivers/gpio/stm32_gpio.c')
-rw-r--r-- | drivers/gpio/stm32_gpio.c | 182 |
1 files changed, 0 insertions, 182 deletions
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c deleted file mode 100644 index c04cef4cb9..0000000000 --- a/drivers/gpio/stm32_gpio.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/stm32.h> -#include <asm/arch/gpio.h> - -DECLARE_GLOBAL_DATA_PTR; - -static const unsigned long io_base[] = { - STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE, - STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE, - STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE -}; - -struct stm32_gpio_regs { - u32 moder; /* GPIO port mode */ - u32 otyper; /* GPIO port output type */ - u32 ospeedr; /* GPIO port output speed */ - u32 pupdr; /* GPIO port pull-up/pull-down */ - u32 idr; /* GPIO port input data */ - u32 odr; /* GPIO port output data */ - u32 bsrr; /* GPIO port bit set/reset */ - u32 lckr; /* GPIO port configuration lock */ - u32 afr[2]; /* GPIO alternate function */ -}; - -#define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15) -#define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \ - x->pupd > 2 || x->speed > 3) - -int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, - const struct stm32_gpio_ctl *ctl) -{ - struct stm32_gpio_regs *gpio_regs; - u32 i; - int rv; - - if (CHECK_DSC(dsc)) { - rv = -EINVAL; - goto out; - } - if (CHECK_CTL(ctl)) { - rv = -EINVAL; - goto out; - } - - gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - - i = (dsc->pin & 0x07) * 4; - clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i); - - i = dsc->pin * 2; - - clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i); - clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i); - clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i); - clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i); - - rv = 0; -out: - return rv; -} - -int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state) -{ - struct stm32_gpio_regs *gpio_regs; - int rv; - - if (CHECK_DSC(dsc)) { - rv = -EINVAL; - goto out; - } - - gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - - if (state) - writel(1 << dsc->pin, &gpio_regs->bsrr); - else - writel(1 << (dsc->pin + 16), &gpio_regs->bsrr); - - rv = 0; -out: - return rv; -} - -int stm32_gpin_get(const struct stm32_gpio_dsc *dsc) -{ - struct stm32_gpio_regs *gpio_regs; - int rv; - - if (CHECK_DSC(dsc)) { - rv = -EINVAL; - goto out; - } - - gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - rv = readl(&gpio_regs->idr) & (1 << dsc->pin); -out: - return rv; -} - -/* Common GPIO API */ - -int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -int gpio_free(unsigned gpio) -{ - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - struct stm32_gpio_dsc dsc; - struct stm32_gpio_ctl ctl; - - dsc.port = stm32_gpio_to_port(gpio); - dsc.pin = stm32_gpio_to_pin(gpio); - ctl.af = STM32_GPIO_AF0; - ctl.mode = STM32_GPIO_MODE_IN; - ctl.otype = STM32_GPIO_OTYPE_PP; - ctl.pupd = STM32_GPIO_PUPD_NO; - ctl.speed = STM32_GPIO_SPEED_50M; - - return stm32_gpio_config(&dsc, &ctl); -} - -int gpio_direction_output(unsigned gpio, int value) -{ - struct stm32_gpio_dsc dsc; - struct stm32_gpio_ctl ctl; - int res; - - dsc.port = stm32_gpio_to_port(gpio); - dsc.pin = stm32_gpio_to_pin(gpio); - ctl.af = STM32_GPIO_AF0; - ctl.mode = STM32_GPIO_MODE_OUT; - ctl.pupd = STM32_GPIO_PUPD_NO; - ctl.speed = STM32_GPIO_SPEED_50M; - - res = stm32_gpio_config(&dsc, &ctl); - if (res < 0) - goto out; - res = stm32_gpout_set(&dsc, value); -out: - return res; -} - -int gpio_get_value(unsigned gpio) -{ - struct stm32_gpio_dsc dsc; - - dsc.port = stm32_gpio_to_port(gpio); - dsc.pin = stm32_gpio_to_pin(gpio); - - return stm32_gpin_get(&dsc); -} - -int gpio_set_value(unsigned gpio, int value) -{ - struct stm32_gpio_dsc dsc; - - dsc.port = stm32_gpio_to_port(gpio); - dsc.pin = stm32_gpio_to_pin(gpio); - - return stm32_gpout_set(&dsc, value); -} |