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| author | Sean Anderson <seanga2@gmail.com> | 2021-04-08 22:13:04 -0400 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-05-14 16:20:47 +0800 |
| commit | d0686a02b98ee264532c25108edc3ba44acc1145 (patch) | |
| tree | adcffc10cdb141a5aabfc93836602df271c71f7c /drivers/ddr/microchip/ddr2.c | |
| parent | 8c12cb3fd80304d4d542d35405aa54ae4a317e9b (diff) | |
| download | u-boot-d0686a02b98ee264532c25108edc3ba44acc1145.tar.gz u-boot-d0686a02b98ee264532c25108edc3ba44acc1145.tar.xz u-boot-d0686a02b98ee264532c25108edc3ba44acc1145.zip | |
clk: k210: Fix PLLs not being enabled
After starting or setting the rate of a PLL, the enable bit must be set.
This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2.c')
0 files changed, 0 insertions, 0 deletions