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| author | Stefan Chulski <stefanc@marvell.com> | 2021-05-03 08:08:45 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-05-20 13:03:30 +0200 |
| commit | 8d3aa376a9e4b410adf4d45cf529c0c2e748165f (patch) | |
| tree | facf3d71346dc5d7cffdc0077a6af226b19decd5 /drivers/ddr/microchip/ddr2.c | |
| parent | 16bacd5e5f49397d2456be0636c9ea64c621ce56 (diff) | |
| download | u-boot-8d3aa376a9e4b410adf4d45cf529c0c2e748165f.tar.gz u-boot-8d3aa376a9e4b410adf4d45cf529c0c2e748165f.tar.xz u-boot-8d3aa376a9e4b410adf4d45cf529c0c2e748165f.zip | |
net: mvpp2: add CP115 port1 10G/5G SFI support
1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
2. Remove XPCS config from SFI mode.
Port1 doesn't XPCS domain, XPCS config should be removed.
Access to Port1 XPCS can cause stall.
3. Add Port1 MPCS configurations.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr/microchip/ddr2.c')
0 files changed, 0 insertions, 0 deletions