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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-03-06 11:14:09 +0100 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-03-24 14:23:18 +0100 |
| commit | b604a41c6bcfb6273e7478089ff3e7b65e233645 (patch) | |
| tree | dc7f3cd77c1fecd3024f0eeb51a281a007fd530e /drivers/ddr/marvell/axp/ddr3_init.c | |
| parent | 8c9ce0807545976c4080621be80dfb02b4ead400 (diff) | |
| download | u-boot-b604a41c6bcfb6273e7478089ff3e7b65e233645.tar.gz u-boot-b604a41c6bcfb6273e7478089ff3e7b65e233645.tar.xz u-boot-b604a41c6bcfb6273e7478089ff3e7b65e233645.zip | |
ram: stm32mp1_ddr: fix self refresh disable during DQS training
DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not
to enter in self refresh mode during the execution of this phase.
Depending on settings, it can be set after the DQS training.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_init.c')
0 files changed, 0 insertions, 0 deletions