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authorRalph Siemsen <ralph.siemsen@linaro.org>2020-09-29 14:52:05 -0400
committerLey Foon Tan <ley.foon.tan@intel.com>2020-10-21 11:45:54 +0800
commitb0b08ce0b7b13520412f1768a0d3290d3c5f50fb (patch)
tree6b073149ad42070403ced9e5eb463e6c5002c3b0 /drivers/ddr/imx/imx8m/ddr_init.c
parent7ec87e4192215815b658c3f8b34e4be010103149 (diff)
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arm: socfpga: fix Gen5 enable of EMAC via FPGA
An earlier conversion from struct to defines introduced two errors, both related to setup of EMAC routed via the FPGA. One of the offsets was incorrect, and the EMAC0/EMAC1 were swapped. The effect of this was rather odd: both ports could operate at gigabit, but one of them would fail to transmit when operating at 100Mbit. Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'drivers/ddr/imx/imx8m/ddr_init.c')
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