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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-01-30 13:07:01 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-02-09 07:50:56 -0500 |
| commit | d661f61847696dc5ac54b397908f886bd3583484 (patch) | |
| tree | 2622d8b40450f89731c8e915cb386cd2bfa5d203 /drivers/clk | |
| parent | 86617dd1402c506a989da74f1f9c13ce1580fa82 (diff) | |
| download | u-boot-d661f61847696dc5ac54b397908f886bd3583484.tar.gz u-boot-d661f61847696dc5ac54b397908f886bd3583484.tar.xz u-boot-d661f61847696dc5ac54b397908f886bd3583484.zip | |
clk: stm32mp1: add IPCC clock
Add support for enable/disable of IPCC clock using AHB3 registers
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk_stm32mp1.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 88f453caa8..a2ab5ed263 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -536,6 +536,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), |