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| author | Hai Pham <hai.pham.ud@renesas.com> | 2020-11-05 22:30:37 +0700 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-05-21 15:00:17 +0200 |
| commit | d413214fb74873721d92ffe27fa63158ee84e469 (patch) | |
| tree | b6f8ff077214dac09d84e7718275fe8c2dd47ac6 /drivers/clk/renesas/renesas-cpg-mssr.c | |
| parent | 406c93c85c78cc86b8b027bd42974a6d3249d39d (diff) | |
| download | u-boot-d413214fb74873721d92ffe27fa63158ee84e469.tar.gz u-boot-d413214fb74873721d92ffe27fa63158ee84e469.tar.xz u-boot-d413214fb74873721d92ffe27fa63158ee84e469.zip | |
clk: renesas: Add register pointers into struct cpg_mssr_info
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda
To support other register layouts in the future, add register pointers
of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Diffstat (limited to 'drivers/clk/renesas/renesas-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/renesas-cpg-mssr.c | 49 |
1 files changed, 4 insertions, 45 deletions
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 0cf80a9866..b1cf7f599c 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -22,47 +22,6 @@ #include "renesas-cpg-mssr.h" -/* - * Module Standby and Software Reset register offets. - * - * If the registers exist, these are valid for SH-Mobile, R-Mobile, - * R-Car Gen2, R-Car Gen3, and RZ/G1. - * These are NOT valid for R-Car Gen1 and RZ/A1! - */ - -/* - * Module Stop Status Register offsets - */ - -static const u16 mstpsr[] = { - 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, - 0x9A0, 0x9A4, 0x9A8, 0x9AC, -}; - -#define MSTPSR(i) mstpsr[i] - - -/* - * System Module Stop Control Register offsets - */ - -static const u16 smstpcr[] = { - 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, - 0x990, 0x994, 0x998, 0x99C, -}; - -#define SMSTPCR(i) smstpcr[i] - - -/* Realtime Module Stop Control Register offsets */ -#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10) - -/* Modem Module Stop Control Register offsets (r8a73a4) */ -#define MMSTPCR(i) (smstpcr[i] + 0x20) - -/* Software Reset Clearing Register offsets */ -#define SRSTCLR(i) (0x940 + (i) * 4) - bool renesas_clk_is_mod(struct clk *clk) { return (clk->id >> 16) == CPG_MOD; @@ -147,11 +106,11 @@ int renesas_clk_endisable(struct clk *clk, void __iomem *base, clkid, reg, bit, enable ? "ON" : "OFF"); if (enable) { - clrbits_le32(base + SMSTPCR(reg), bitmask); - return wait_for_bit_le32(base + MSTPSR(reg), + clrbits_le32(base + info->control_regs[reg], bitmask); + return wait_for_bit_le32(base + info->status_regs[reg], bitmask, 0, 100, 0); } else { - setbits_le32(base + SMSTPCR(reg), bitmask); + setbits_le32(base + info->control_regs[reg], bitmask); return 0; } } @@ -165,7 +124,7 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info) /* Stop module clock */ for (i = 0; i < info->mstp_table_size; i++) { - clrsetbits_le32(base + SMSTPCR(i), + clrsetbits_le32(base + info->control_regs[i], info->mstp_table[i].sdis, info->mstp_table[i].sen); clrsetbits_le32(base + RMSTPCR(i), |