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| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-01-15 00:58:35 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-01-24 23:27:22 +0100 |
| commit | ff50b323b325b0bf44753682656d28c76e9dfda1 (patch) | |
| tree | 7572c2d5747a6e390702b23674accb800ef7808b /drivers/clk/renesas/r8a7796-cpg-mssr.c | |
| parent | 58f1788f47b3c1da24dc825d5994b88be82c11c1 (diff) | |
| download | u-boot-ff50b323b325b0bf44753682656d28c76e9dfda1.tar.gz u-boot-ff50b323b325b0bf44753682656d28c76e9dfda1.tar.xz u-boot-ff50b323b325b0bf44753682656d28c76e9dfda1.zip | |
clk: renesas: Split SMSTPCR and RMSTPCR tables
The Gen2 requires setting RMSTPCR before booting, while on Gen3 this
is thus far always zero. Split the tables so the RMSTPCR can be set
too.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/clk/renesas/r8a7796-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a7796-cpg-mssr.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 80e07dacce..fb811e943e 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -289,12 +289,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { }; static const struct mstp_stop_table r8a7796_mstp_table[] = { - { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 }, - { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 }, - { 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 }, - { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 }, - { 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 }, - { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, + { 0x00200000, 0x0, 0x00200000, 0 }, + { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, + { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 }, + { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, + { 0x80000184, 0x180, 0x80000184, 0 }, + { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 }, + { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, + { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, + { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 }, + { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 }, + { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, + { 0x000000B7, 0x0, 0x000000B7, 0 }, }; static const void *r8a7796_get_pll_config(const u32 cpg_mode) |