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| author | Fabrice Gasnier <fabrice.gasnier@st.com> | 2018-04-26 17:00:47 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-08 09:07:39 -0400 |
| commit | f198bbac6695ecaac281e8dc5c5d74464ac82b3e (patch) | |
| tree | f573683eb8dbd3aa38ce01cb97b5af72eafb2d1c /drivers/clk/clk_stm32mp1.c | |
| parent | 93cf0ae7758d66475963a6b2186e41c51a1840aa (diff) | |
| download | u-boot-f198bbac6695ecaac281e8dc5c5d74464ac82b3e.tar.gz u-boot-f198bbac6695ecaac281e8dc5c5d74464ac82b3e.tar.xz u-boot-f198bbac6695ecaac281e8dc5c5d74464ac82b3e.zip | |
clk: stm32mp1: Add VREF clock gating
Add VREF clock gating, that may be used by STM32 VREFBUF regulator.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'drivers/clk/clk_stm32mp1.c')
| -rw-r--r-- | drivers/clk/clk_stm32mp1.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index ed32585eb0..1a77eba39c 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -100,6 +100,7 @@ #define RCC_USBCKSELR 0x91C #define RCC_MP_APB1ENSETR 0xA00 #define RCC_MP_APB2ENSETR 0XA08 +#define RCC_MP_APB3ENSETR 0xA10 #define RCC_MP_AHB2ENSETR 0xA18 #define RCC_MP_AHB4ENSETR 0xA28 @@ -508,6 +509,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), + STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3), + STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), |