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| author | Marek Vasut <marex@denx.de> | 2018-07-31 17:58:07 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-08-13 22:35:42 +0200 |
| commit | f9f016adcdc686bf3c50399492d579a024ed7520 (patch) | |
| tree | a298dde4114bab882127210853c218eac3ab8051 /drivers/clk/Makefile | |
| parent | ccc97432adf50156da86132ad75e3a99c9c0d3eb (diff) | |
| download | u-boot-f9f016adcdc686bf3c50399492d579a024ed7520.tar.gz u-boot-f9f016adcdc686bf3c50399492d579a024ed7520.tar.xz u-boot-f9f016adcdc686bf3c50399492d579a024ed7520.zip | |
clk: socfpga: Add initial Arria10 clock driver
Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.
Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'drivers/clk/Makefile')
| -rw-r--r-- | drivers/clk/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 146283c723..034bf44078 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -11,6 +11,7 @@ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MESON) += clk_meson.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_SOCFPGA) += altera/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_MVEBU) += mvebu/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o |