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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-04-18 17:32:40 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@st.com> | 2019-05-23 11:36:46 +0200 |
| commit | bb7288ef1c170302d51c666087b65df38e3aab2a (patch) | |
| tree | 26bfff355c0ef929097d413dbfebc6595114ff67 /doc/device-tree-bindings/clock/st,stm32mp1.txt | |
| parent | ee7d7723706efd935b669951cea102974c645065 (diff) | |
| download | u-boot-bb7288ef1c170302d51c666087b65df38e3aab2a.tar.gz u-boot-bb7288ef1c170302d51c666087b65df38e3aab2a.tar.xz u-boot-bb7288ef1c170302d51c666087b65df38e3aab2a.zip | |
stm32mp1: psci: add synchronization with ROM code
Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER
to synchronize the core1 boot sequence requested by
core0 in psci_cpu_on():
- a initial interruption is needed in ROM code after
RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off)
- the ROM code set to 0 the 2 registers
+ TAMP_BACKUP_BRANCH_ADDRESS
+ TAMP_BACKUP_MAGIC_NUMBER
when magic is not egual to
BOOT_API_A7_CORE0_MAGIC_NUMBER
This patch solve issue for cpu1 restart in kernel.
echo 0 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu1/online
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'doc/device-tree-bindings/clock/st,stm32mp1.txt')
0 files changed, 0 insertions, 0 deletions