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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-03-06 11:14:07 +0100 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-03-24 14:20:50 +0100 |
| commit | 27e7b4edeabe87be1cb9dc549b2f7d91c1f3e3a7 (patch) | |
| tree | a87c6a53f1a595d01189520e06574c4f839f1ef4 /doc/arch | |
| parent | f711d1f0804e01586b8f68af81cde6a15b58d427 (diff) | |
| download | u-boot-27e7b4edeabe87be1cb9dc549b2f7d91c1f3e3a7.tar.gz u-boot-27e7b4edeabe87be1cb9dc549b2f7d91c1f3e3a7.tar.xz u-boot-27e7b4edeabe87be1cb9dc549b2f7d91c1f3e3a7.zip | |
ram: stm32mp1: tuning: deactivate derating during BIST test
The derating (timing parameter derating using MR4 read value)
can't be activated during BIST test, as the MR4 read answer will
be not understood by BIST (BISTGSR.BDONE bit stay at 0,
BISTWCSR.DXWCNT = 0x206 instead of BISTWCR.BWCNT = 0x200).
This patch only impacts the tuning on LPDDR2/LPDDR3,
if derateen.derate_enable = 1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'doc/arch')
0 files changed, 0 insertions, 0 deletions