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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-01-30 13:07:06 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-02-09 07:50:57 -0500 |
| commit | bbd108a08225b1239b1ec1c10e8131fba6a3a95a (patch) | |
| tree | 3324114ed3c850227bebde0f28d258b303028b50 /doc/README.bus_vcxk | |
| parent | e74b74c52876d776dda7a7ee5e2a8d555eaa5c4f (diff) | |
| download | u-boot-bbd108a08225b1239b1ec1c10e8131fba6a3a95a.tar.gz u-boot-bbd108a08225b1239b1ec1c10e8131fba6a3a95a.tar.xz u-boot-bbd108a08225b1239b1ec1c10e8131fba6a3a95a.zip | |
clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'doc/README.bus_vcxk')
0 files changed, 0 insertions, 0 deletions