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authorwdenk <wdenk>2004-06-06 21:35:06 +0000
committerwdenk <wdenk>2004-06-06 21:35:06 +0000
commit1114257c9df3fa3db39ff55dd03d1f7cbc5c0603 (patch)
tree7d62ed142cf3c00aea35e518ed28dc9f5c6887fd /cpu/mpc8xx
parentd7a04603ae9c85d496b3991f29dbb8ea339ace49 (diff)
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Patch by Yuli Barcohen, 19 Apr 2004:
- Rename DUET_ADS to MPC885ADS - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY - Clean up FADS family port to use the new defines
Diffstat (limited to 'cpu/mpc8xx')
-rw-r--r--cpu/mpc8xx/fec.c14
-rw-r--r--cpu/mpc8xx/speed.c39
2 files changed, 35 insertions, 18 deletions
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index 39fe690316..c6b84fae16 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -388,7 +388,7 @@ static void fec_pin_init(int fecidx)
fecp->fec_mii_speed <<= 1;
#endif
-#if defined(CONFIG_DUET) && defined(WANT_MII)
+#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
/* use MDC for MII */
immr->im_ioport.iop_pdpar |= 0x0080;
immr->im_ioport.iop_pddir &= ~0x0080;
@@ -397,7 +397,7 @@ static void fec_pin_init(int fecidx)
if (fecidx == 0) {
#if defined(CONFIG_ETHER_ON_FEC1)
-#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
+#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII)
@@ -489,7 +489,7 @@ static void fec_pin_init(int fecidx)
#if defined(CONFIG_ETHER_ON_FEC2)
-#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
+#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII)
@@ -516,7 +516,7 @@ static void fec_pin_init(int fecidx)
immr->im_cpm.cp_cptr &= ~0x00000028;
#endif /* CONFIG_RMII */
-#endif /* CONFIG_DUET */
+#endif /* CONFIG_MPC885_FAMILY */
#endif /* CONFIG_ETHER_ON_FEC2 */
@@ -533,7 +533,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
if (efis->ether_index == 0) {
#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
-#if defined(CONFIG_DUET_ADS)
+#if defined(CONFIG_MPC885ADS)
*(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
#else
/* configure FADS for fast (FEC) ethernet, half-duplex */
@@ -553,7 +553,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
*bcsr4 |= BCSR4_FETHRST;
udelay (10);
}
-#endif /* CONFIG_DUET_ADS */
+#endif /* CONFIG_MPC885ADS */
#endif /* CONFIG_FADS */
}
@@ -948,7 +948,7 @@ void mii_init (void)
*/
fecp->fec_ievent = 0xffc0;
- /* Setup the pin configuration of the FEC(s)
+ /* Setup the pin configuration of the FEC(s)
*/
fec_pin_init(ether_fcc_info[i].ether_index);
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 165705cea9..cc011efa4d 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -90,7 +90,7 @@ unsigned long measure_gclk(void)
ulong timer2_val;
ulong msr_val;
-#ifdef CONFIG_MPC866_et_al
+#ifdef CFG_8XX_XIN
/* dont use OSCM, only use EXTCLK/512 */
immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
@@ -162,7 +162,7 @@ unsigned long measure_gclk(void)
timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
immr->im_sit.sit_piscr &= ~PISCR_PTE;
-#if defined(CONFIG_MPC866_et_al)
+#if defined(CFG_8XX_XIN)
/* not using OSCM, using XIN, so scale appropriately */
return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
#else
@@ -183,22 +183,39 @@ int get_clocks (void)
{
DECLARE_GLOBAL_DATA_PTR;
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
-#ifndef CONFIG_8xx_GCLK_FREQ
- gd->cpu_clk = measure_gclk();
-#else /* CONFIG_8xx_GCLK_FREQ */
+ uint immr = get_immr (0); /* Return full IMMR contents */
+ volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
+ uint sccr = immap->im_clkrst.car_sccr;
/*
* If for some reason measuring the gclk frequency won't
* work, we return the hardwired value.
* (For example, the cogent CMA286-60 CPU module has no
* separate oscillator for PITRTCLK)
*/
-
+#if defined(CONFIG_8xx_GCLK_FREQ)
gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
-
+#elif defined(CONFIG_8xx_OSCLK)
+#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
+ uint pll = immap->im_clkrst.car_plprcr;
+ uint clk;
+
+ if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
+ clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
+ (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
+ (1<<PLPRCR_val(S));
+ } else {
+ clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
+ }
+ if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
+ gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
+ } else { /* High frequency division factor is used */
+ gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
+ }
+#else
+ gd->cpu_clk = measure_gclk();
#endif /* CONFIG_8xx_GCLK_FREQ */
- if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
+ if ((sccr & SCCR_EBDF11) == 0) {
/* No Bus Divider active */
gd->bus_clk = gd->cpu_clk;
} else {
@@ -209,7 +226,7 @@ int get_clocks (void)
return (0);
}
-#else /* CONFIG_MPC866_et_al */
+#else /* CONFIG_MPC866_FAMILY */
static long init_pll_866 (long clk);
@@ -345,7 +362,7 @@ static long init_pll_866 (long clk)
return (n);
}
-#endif /* CONFIG_MPC866_et_al */
+#endif /* CONFIG_MPC866_FAMILY */
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
/*