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| author | Marek Behún <marek.behun@nic.cz> | 2020-04-15 00:59:18 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-04-22 14:28:15 +0200 |
| commit | 239f424f497dcda32322d3ee990f20d26a5a2f47 (patch) | |
| tree | 03d98bd80c8bde4f47f41a6d78a85494c081f5e0 /configs/turris_omnia_defconfig | |
| parent | bdcb29960e3a9558803632783b922f26993d219e (diff) | |
| download | u-boot-239f424f497dcda32322d3ee990f20d26a5a2f47.tar.gz u-boot-239f424f497dcda32322d3ee990f20d26a5a2f47.tar.xz u-boot-239f424f497dcda32322d3ee990f20d26a5a2f47.zip | |
clk: armada-37xx-periph: fix DDR PHY clock divider values
Register value table for DDR PHY clock divider are wrong. They should be
0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current
values do not make sense, since 2 cannot be achieved, because the
register is only 1 bit long (mask is set to 1).
This fixes clk dump reporting DDR PHY clock rate differently from Linux.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'configs/turris_omnia_defconfig')
0 files changed, 0 insertions, 0 deletions