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authorMarek Vasut <marex@denx.de>2015-07-12 15:23:28 +0200
committerMarek Vasut <marex@denx.de>2015-08-08 14:14:09 +0200
commit7599b53dc1a1c89457a755858d4b6946e0e7fadd (patch)
treed1123227a547d96eb662a5fcd5a7f119bd38116d /configs/socfpga_cyclone5_defconfig
parent6ab00db226296b9512baf00d1dc1728e599e385d (diff)
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arm: socfpga: config: Move SPL GD and malloc to RAM
Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'configs/socfpga_cyclone5_defconfig')
-rw-r--r--configs/socfpga_cyclone5_defconfig3
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 75ed347f0e..ae3a1dea91 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -17,3 +17,6 @@ CONFIG_SPL_SIMPLE_BUS=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000