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| author | Kever Yang <kever.yang@rock-chips.com> | 2019-10-23 11:10:36 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-11-10 20:40:20 +0800 |
| commit | 4b294886d03e9989d6ff163eef04da4927f75952 (patch) | |
| tree | c36c6f85334e8865bdc8c82d5953dcfe410ecebc /configs/evb-px5_defconfig | |
| parent | ae2500f89a8de636a2a23187010fa57f44ac3bd3 (diff) | |
| download | u-boot-4b294886d03e9989d6ff163eef04da4927f75952.tar.gz u-boot-4b294886d03e9989d6ff163eef04da4927f75952.tar.xz u-boot-4b294886d03e9989d6ff163eef04da4927f75952.zip | |
rockchip: evb-px5: defconfig: no need to reserve IRAM for SPL
We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.
Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.
The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'configs/evb-px5_defconfig')
| -rw-r--r-- | configs/evb-px5_defconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 5a06b2a99f..1d2d8e1078 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3368=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 CONFIG_TPL_LIBCOMMON_SUPPORT=y CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |