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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2020-07-16 18:09:25 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-09-24 08:27:44 -0400 |
| commit | 6c9e68e8604150b263b191cfb51b102a00eb055d (patch) | |
| tree | 773570f68a72a3788585ed81ddbc6e5b9065c6cc /configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | |
| parent | 613e49bb91a4d367e64b6c644dd7e5a9e49f3063 (diff) | |
| download | u-boot-6c9e68e8604150b263b191cfb51b102a00eb055d.tar.gz u-boot-6c9e68e8604150b263b191cfb51b102a00eb055d.tar.xz u-boot-6c9e68e8604150b263b191cfb51b102a00eb055d.zip | |
configs: P2020RDB: Enable DM_ETH config
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig')
| -rw-r--r-- | configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 68c5b54591..67c3711ad2 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_FIXED=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y @@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_DM_MDIO=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y |