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authorMarek Vasut <marex@denx.de>2017-05-02 20:27:41 +0200
committerTom Rini <trini@konsulko.com>2017-06-29 13:30:28 -0400
commitae625ae5a14f63400b8e5ee901a27248037a2339 (patch)
tree943eb63d7f3989a5eaa893019e516bf5209d5404 /configs/M54418TWR_nand_mii_defconfig
parentf1d56dffd7f1a112482cdbe4e0ac2076e1eb3fe1 (diff)
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ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding
According to the datasheet, sequential mapping is used for DDR SDRAM, while interleaved mapping is used for regular SDRAM. Incorrect configuration of this bit does indeed cause sporadic memory instability. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com>
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