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| author | JC Kuo <jckuo@nvidia.com> | 2020-03-26 16:10:09 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2020-04-02 14:30:01 -0700 |
| commit | d491dc09e4cfb7e513d3d6f448d811f1297753d9 (patch) | |
| tree | df53d53d39048ade69bc6e351ee8c78b9aff5fc7 /cmd/mfsl.c | |
| parent | 9eb15cbe5c94fca24519b5d89d934eeb34a68e5d (diff) | |
| download | u-boot-d491dc09e4cfb7e513d3d6f448d811f1297753d9.tar.gz u-boot-d491dc09e4cfb7e513d3d6f448d811f1297753d9.tar.xz u-boot-d491dc09e4cfb7e513d3d6f448d811f1297753d9.zip | |
t210: do not enable PLLE and UPHY PLL HW PWRSEQ
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.
Adds call to board_cleanup_before_linux to facilitate this.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'cmd/mfsl.c')
0 files changed, 0 insertions, 0 deletions