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authorTom Rini <trini@konsulko.com>2018-04-15 08:43:50 -0400
committerTom Rini <trini@konsulko.com>2018-04-15 08:43:50 -0400
commitebca902aeb3af3eaedd2787928184ad84a86b98f (patch)
tree20081e5c2cff3760d1ece3602823a3e3ff6d47d0 /board
parentdf13a44377b36f438d15de06b07ad4645b89cf4f (diff)
parentb4e9bdcd05ac83146ad16802a94db3e78f530d1a (diff)
downloadu-boot-ebca902aeb3af3eaedd2787928184ad84a86b98f.tar.gz
u-boot-ebca902aeb3af3eaedd2787928184ad84a86b98f.tar.xz
u-boot-ebca902aeb3af3eaedd2787928184ad84a86b98f.zip
Merge git://git.denx.de/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/mx31ads/Kconfig15
-rw-r--r--board/freescale/mx31ads/MAINTAINERS6
-rw-r--r--board/freescale/mx31ads/Makefile8
-rw-r--r--board/freescale/mx31ads/lowlevel_init.S268
-rw-r--r--board/freescale/mx31ads/mx31ads.c114
-rw-r--r--board/freescale/mx31ads/u-boot.lds110
-rw-r--r--board/ge/bx50v3/bx50v3.c45
-rw-r--r--board/imx31_phycore/Kconfig12
-rw-r--r--board/imx31_phycore/MAINTAINERS11
-rw-r--r--board/imx31_phycore/Makefile9
-rw-r--r--board/imx31_phycore/imx31_phycore.c154
-rw-r--r--board/imx31_phycore/lowlevel_init.S88
-rw-r--r--board/k+p/bootscripts/tpcboot.cmd96
-rw-r--r--board/k+p/kp_imx6q_tpc/Kconfig12
-rw-r--r--board/k+p/kp_imx6q_tpc/MAINTAINERS6
-rw-r--r--board/k+p/kp_imx6q_tpc/Makefile11
-rw-r--r--board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c302
-rw-r--r--board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c338
-rw-r--r--board/solidrun/mx6cuboxi/mx6cuboxi.c3
-rw-r--r--board/wandboard/wandboard.c1
-rw-r--r--board/warp7/warp7.c14
21 files changed, 808 insertions, 815 deletions
diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig
deleted file mode 100644
index eeeb6f490f..0000000000
--- a/board/freescale/mx31ads/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX31ADS
-
-config SYS_BOARD
- default "mx31ads"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "mx31ads"
-
-endif
diff --git a/board/freescale/mx31ads/MAINTAINERS b/board/freescale/mx31ads/MAINTAINERS
deleted file mode 100644
index 5f6ec268c7..0000000000
--- a/board/freescale/mx31ads/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX31ADS BOARD
-#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-S: Orphan (since 2013-09)
-F: board/freescale/mx31ads/
-F: include/configs/mx31ads.h
-F: configs/mx31ads_defconfig
diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile
deleted file mode 100644
index 5e1440d596..0000000000
--- a/board/freescale/mx31ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mx31ads.o
-obj-y += lowlevel_init.o
diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S
deleted file mode 100644
index fcb5549d77..0000000000
--- a/board/freescale/mx31ads/lowlevel_init.S
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-/* RedBoot: AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- ldr r0, =0x43F00000
- ldr r1, =0x77777777
- str r1, [r0, #0x00]
- str r1, [r0, #0x04]
- ldr r0, =0x53F00000
- str r1, [r0, #0x00]
- str r1, [r0, #0x04]
-
- /*
- * Clear the on and off peripheral modules Supervisor Protect bit
- * for SDMA to access them. Did not change the AIPS control registers
- * (offset 0x20) access type
- */
- ldr r0, =0x43F00000
- ldr r1, =0x0
- str r1, [r0, #0x40]
- str r1, [r0, #0x44]
- str r1, [r0, #0x48]
- str r1, [r0, #0x4C]
- ldr r1, [r0, #0x50]
- and r1, r1, #0x00FFFFFF
- str r1, [r0, #0x50]
-
- ldr r0, =0x53F00000
- ldr r1, =0x0
- str r1, [r0, #0x40]
- str r1, [r0, #0x44]
- str r1, [r0, #0x48]
- str r1, [r0, #0x4C]
- ldr r1, [r0, #0x50]
- and r1, r1, #0x00FFFFFF
- str r1, [r0, #0x50]
-.endm /* init_aips */
-
-/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
- ldr r0, =0x43F04000
- /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
- ldr r1, =0x00302154
- str r1, [r0, #0x000] /* for S0 */
- str r1, [r0, #0x100] /* for S1 */
- str r1, [r0, #0x200] /* for S2 */
- str r1, [r0, #0x300] /* for S3 */
- str r1, [r0, #0x400] /* for S4 */
- /* SGPCR - always park on last master */
- ldr r1, =0x10
- str r1, [r0, #0x010] /* for S0 */
- str r1, [r0, #0x110] /* for S1 */
- str r1, [r0, #0x210] /* for S2 */
- str r1, [r0, #0x310] /* for S3 */
- str r1, [r0, #0x410] /* for S4 */
- /* MGPCR - restore default values */
- ldr r1, =0x0
- str r1, [r0, #0x800] /* for M0 */
- str r1, [r0, #0x900] /* for M1 */
- str r1, [r0, #0xA00] /* for M2 */
- str r1, [r0, #0xB00] /* for M3 */
- str r1, [r0, #0xC00] /* for M4 */
- str r1, [r0, #0xD00] /* for M5 */
-.endm /* init_max */
-
-/* RedBoot: M3IF setup */
-.macro init_m3if
- /* Configure M3IF registers */
- ldr r1, =0xB8003000
- /*
- * M3IF Control Register (M3IFCTL)
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
- * ------------
- * 0x00000040
- */
- ldr r0, =0x00000040
- str r0, [r1] /* M3IF control reg */
-.endm /* init_m3if */
-
-/* RedBoot: To support 133MHz DDR */
-.macro init_drive_strength
- /*
- * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
- * in SW_PAD_CTL registers
- */
-
- /* SDCLK */
- ldr r1, =0x43FAC200
- ldr r0, [r1, #0x6C]
- bic r0, r0, #(1 << 12)
- str r0, [r1, #0x6C]
-
- /* CAS */
- ldr r0, [r1, #0x70]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x70]
-
- /* RAS */
- ldr r0, [r1, #0x74]
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x74]
-
- /* CS2 (CSD0) */
- ldr r0, [r1, #0x7C]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x7C]
-
- /* DQM3 */
- ldr r0, [r1, #0x84]
- bic r0, r0, #(1 << 22)
- str r0, [r1, #0x84]
-
- /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
-pad_loop:
- ldr r0, [r1, #0x88]
- bic r0, r0, #(1 << 22)
- bic r0, r0, #(1 << 12)
- bic r0, r0, #(1 << 2)
- str r0, [r1, #0x88]
- add r1, r1, #4
- subs r2, r2, #0x1
- bne pad_loop
-.endm /* init_drive_strength */
-
-/* CPLD on CS4 setup */
-.macro init_cs4
- ldr r0, =WEIM_BASE
- ldr r1, =0x0000D843
- str r1, [r0, #0x40]
- ldr r1, =0x22252521
- str r1, [r0, #0x44]
- ldr r1, =0x22220A00
- str r1, [r0, #0x48]
-.endm /* init_cs4 */
-
-.globl lowlevel_init
-lowlevel_init:
-
- /* Redboot initializes very early AIPS, what for?
- * Then it also initializes Multi-Layer AHB Crossbar Switch,
- * M3IF */
- /* Also setup the Peripheral Port Remap register inside the core */
- ldr r0, =0x40000015 /* start from AIPS 2GB region */
- mcr p15, 0, r0, c15, c2, 4
-
- init_aips
-
- init_max
-
- init_m3if
-
- init_drive_strength
-
- init_cs4
-
- /* Image Processing Unit: */
- /* Too early to switch display on? */
- REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
- /* Clock Control Module: */
- REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
-
- /* PBC CPLD on CS4 */
- mov r1, #CS4_BASE
- ldrh r1, [r1, #0x2]
- /* Is 27MHz switch set? */
- ands r1, r1, #0x10
-
- /* 532-133-66.5 */
- ldr r0, =CCM_BASE
- ldr r1, =0xFF871D58
- /* PDR0 */
- str r1, [r0, #0x4]
- ldreq r1, MPCTL_PARAM_532
- ldrne r1, MPCTL_PARAM_532_27
- /* MPCTL */
- str r1, [r0, #0x10]
-
- /* Set UPLL=240MHz, USB=60MHz */
- ldr r1, =0x49FCFE7F
- /* PDR1 */
- str r1, [r0, #0x8]
- ldreq r1, UPCTL_PARAM_240
- ldrne r1, UPCTL_PARAM_240_27
- /* UPCTL */
- str r1, [r0, #0x14]
- /* default CLKO to 1/8 of the ARM core */
- mov r1, #0x000002C0
- add r1, r1, #0x00000006
- /* COSR */
- str r1, [r0, #0x1c]
-
- /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
-/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
-
- /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
-/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
- /* Default: 1, 4, 12, 1 */
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
- /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
- REG 0xB8001010, 0x00000004
- REG 0xB8001004, 0x006ac73a
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- REG 0xB8001000, 0x82226080
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
- mov pc, lr
-
-MPCTL_PARAM_532:
- .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
-MPCTL_PARAM_532_27:
- .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
-UPCTL_PARAM_240:
- .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
-UPCTL_PARAM_240_27:
- .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
deleted file mode 100644
index ad89cb021d..0000000000
--- a/board/freescale/mx31ads/mx31ads.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_early_init_f(void)
-{
- int i;
-
- /* CS0: Nor Flash */
- /*
- * CS0L and CS0A values are from the RedBoot sources by Freescale
- * and are also equal to those used by Sascha Hauer for the Phytec
- * i.MX31 board. CS0U is just a slightly optimized hardware default:
- * the only non-zero field "Wait State Control" is set to half the
- * default value.
- */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* SPI2 */
- mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
- mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
- mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
- mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
- mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
- mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
- mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
-
- /* start SPI2 clock */
- __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-
- /* PBC setup */
- /* Enable UART transceivers also reset the Ethernet/external UART */
- readw(CS4_BASE + 4);
-
- writew(0x8023, CS4_BASE + 4);
-
- /* RedBoot also has an empty loop with 100000 iterations here -
- * clock doesn't run yet */
- for (i = 0; i < 100000; i++)
- ;
-
- /* Clear the reset, toggle the LEDs */
- writew(0xDF, CS4_BASE + 6);
-
- /* clock still doesn't run */
- for (i = 0; i < 100000; i++)
- ;
-
- /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
- readb(CS4_BASE + 8);
- readb(CS4_BASE + 7);
- readb(CS4_BASE + 8);
- readb(CS4_BASE + 7);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
-
- return 0;
-}
-
-int checkboard(void)
-{
- printf("Board: MX31ADS\n");
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
deleted file mode 100644
index 71a63f188e..0000000000
--- a/board/freescale/mx31ads/u-boot.lds
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- * (.vectors)
- arch/arm/cpu/arm1136/start.o (.text*)
- board/freescale/mx31ads/built-in.o (.text*)
- arch/arm/lib/built-in.o (.text*)
- net/built-in.o (.text*)
- drivers/mtd/built-in.o (.text*)
-
- . = DEFINED(env_offset) ? env_offset : .;
- env/embedded.o(.text*)
-
- *(.text*)
- }
- . = ALIGN(4);
- .rodata : { *(.rodata*) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index c7a29185bf..46321ae666 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -786,23 +786,6 @@ int board_late_init(void)
add_board_boot_modes(board_boot_modes);
#endif
-#ifdef CONFIG_VIDEO_IPUV3
- /* We need at least 200ms between power on and backlight on
- * as per specifications from CHI MEI */
- mdelay(250);
-
- /* enable backlight PWM 1 */
- pwm_init(0, 0, 0);
-
- /* duty cycle 5000000ns, period: 5000000ns */
- pwm_config(0, 5000000, 5000000);
-
- /* Backlight Power */
- gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
-
- pwm_enable(0);
-#endif
-
/* board specific pmic init */
pmic_init();
@@ -843,3 +826,31 @@ int checkboard(void)
printf("BOARD: %s\n", CONFIG_BOARD_NAME);
return 0;
}
+
+static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_VIDEO_IPUV3
+ /* We need at least 200ms between power on and backlight on
+ * as per specifications from CHI MEI */
+ mdelay(250);
+
+ /* enable backlight PWM 1 */
+ pwm_init(0, 0, 0);
+
+ /* duty cycle 5000000ns, period: 5000000ns */
+ pwm_config(0, 5000000, 5000000);
+
+ /* Backlight Power */
+ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+
+ pwm_enable(0);
+#endif
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ bx50_backlight_enable, 1, 1, do_backlight_enable,
+ "enable Bx50 backlight",
+ ""
+);
diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig
deleted file mode 100644
index e897ee1c3a..0000000000
--- a/board/imx31_phycore/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET
-
-config SYS_BOARD
- default "imx31_phycore"
-
-config SYS_SOC
- default "mx31"
-
-config SYS_CONFIG_NAME
- default "imx31_phycore"
-
-endif
diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS
deleted file mode 100644
index 41f6cae81b..0000000000
--- a/board/imx31_phycore/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-IMX31_PHYCORE BOARD
-#M: -
-S: Maintained
-F: board/imx31_phycore/
-F: include/configs/imx31_phycore.h
-F: configs/imx31_phycore_defconfig
-
-IMX31_PHYCORE_EET BOARD
-#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-S: Orphan (since 2013-09)
-F: configs/imx31_phycore_eet_defconfig
diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile
deleted file mode 100644
index e781c13936..0000000000
--- a/board/imx31_phycore/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := imx31_phycore.o
-obj-y += lowlevel_init.o
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
deleted file mode 100644
index 653246615f..0000000000
--- a/board/imx31_phycore/imx31_phycore.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <s6e63d6.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/mach-types.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-int board_init(void)
-{
-
- gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */
- gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- /* CS0: Nor Flash */
- static const struct mxc_weimcs cs0 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
- };
-
- /* CS1: Network Controller */
- static const struct mxc_weimcs cs1 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
- };
-
- /* CS4: SRAM */
- static const struct mxc_weimcs cs4 = {
- /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
- CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
- /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
- CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
- /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
- CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
- };
-
- mxc_setup_weimcs(0, &cs0);
- mxc_setup_weimcs(1, &cs1);
- mxc_setup_weimcs(4, &cs4);
-
- /* setup pins for UART1 */
- mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
- mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
- mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
- mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
- /* setup pins for I2C2 (for EEPROM, RTC) */
- mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
- mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_S6E63D6
- struct s6e63d6 data = {
- /*
- * See comment in mxc_spi.c::decode_cs() for .cs field format.
- * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
- * 2 of the SPI controller #1, since it is unused.
- */
- .cs = 2 | (57 << 8),
- .bus = 0,
- .id = 0,
- };
- int ret;
-
- /* SPI1 */
- mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
- mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
- mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
- mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
- mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
- mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
- mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
-
- /* start SPI1 clock */
- __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
-
- /* GPIO 57 */
- /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
- mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
-
- /* SPI1 CS2 is free */
- ret = s6e63d6_init(&data);
- if (ret)
- return ret;
-
- /*
- * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
- * OLED display connected to a S6E63D6 SPI display controller in the
- * 18 bit RGB mode
- */
- s6e63d6_index(&data, 2);
- s6e63d6_param(&data, 0x0182);
- s6e63d6_index(&data, 3);
- s6e63d6_param(&data, 0x8130);
- s6e63d6_index(&data, 0x10);
- s6e63d6_param(&data, 0x0000);
- s6e63d6_index(&data, 5);
- s6e63d6_param(&data, 0x0001);
- s6e63d6_index(&data, 0x22);
-#endif
- return 0;
-}
-#endif
-
-int checkboard (void)
-{
- printf("Board: Phytec phyCore i.MX31\n");
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
deleted file mode 100644
index 6ea3878ef9..0000000000
--- a/board/imx31_phycore/lowlevel_init.S
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
- ldr r2, =\reg
- ldr r3, =\val
- str r3, [r2]
-.endm
-
-.macro REG8 reg, val
- ldr r2, =\reg
- ldr r3, =\val
- strb r3, [r2]
-.endm
-
-.macro DELAY loops
- ldr r2, =\loops
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-
- REG IPU_CONF, IPU_CONF_DI_EN
- REG CCM_CCMR, 0x074B0BF5
-
- DELAY 0x40000
-
- REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
- REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
-
- REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
-
- REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
-
- REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
-
- REG 0x43FAC26C, 0 /* SDCLK */
- REG 0x43FAC270, 0 /* CAS */
- REG 0x43FAC274, 0 /* RAS */
- REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
- REG 0x43FAC284, 0 /* DQM3 */
- REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
- REG 0x43FAC28C, 0
- REG 0x43FAC290, 0
- REG 0x43FAC294, 0
- REG 0x43FAC298, 0
- REG 0x43FAC29C, 0
- REG 0x43FAC2A0, 0
- REG 0x43FAC2A4, 0
- REG 0x43FAC2A8, 0
- REG 0x43FAC2AC, 0
- REG 0x43FAC2B0, 0
- REG 0x43FAC2B4, 0
- REG 0x43FAC2B8, 0
- REG 0x43FAC2BC, 0
- REG 0x43FAC2C0, 0
- REG 0x43FAC2C4, 0
- REG 0x43FAC2C8, 0
- REG 0x43FAC2CC, 0
- REG 0x43FAC2D0, 0
- REG 0x43FAC2D4, 0
- REG 0x43FAC2D8, 0
- REG 0x43FAC2DC, 0
- REG 0xB8001010, 0x00000004
- REG 0xB8001004, 0x006ac73a
- REG 0xB8001000, 0x92100000
- REG 0x80000f00, 0x12344321
- REG 0xB8001000, 0xa2100000
- REG 0x80000000, 0x12344321
- REG 0x80000000, 0x12344321
- REG 0xB8001000, 0xb2100000
- REG8 0x80000033, 0xda
- REG8 0x81000000, 0xff
- REG 0xB8001000, 0x82226080
- REG 0x80000000, 0xDEADBEEF
- REG 0xB8001010, 0x0000000c
-
- mov pc, lr
diff --git a/board/k+p/bootscripts/tpcboot.cmd b/board/k+p/bootscripts/tpcboot.cmd
new file mode 100644
index 0000000000..f6d59a1186
--- /dev/null
+++ b/board/k+p/bootscripts/tpcboot.cmd
@@ -0,0 +1,96 @@
+#
+# Copyright (C) 2018
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+#
+#
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d tpcboot.cmd boot.scr
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+
+# Input envs (to be set in environment)
+# Mandatory:
+# kernel_file = "fitImage"
+# boardname = "XXXX" // set automatically in u-boot
+# boardsoc = "imx6q" // set automatically in u-boot
+#
+# Optional:
+# bootcmd_force = "nfs" "tftp_kernel"
+# If not set - eMMC/SD boot
+
+# Generic setup
+setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw"
+setenv displayargs ""
+setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \
+ ${displayargs}"
+setenv boot_fitImage "
+ setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
+ setenv itbcfg "\"#\${fdt_conf}\"";
+ print itbcfg;
+ bootm '${loadaddr}${itbcfg}';"
+
+#------------------------------------------------------------
+#
+# Provide default 'bootcmd' command
+#------------------------------------------------------------
+setenv bootcmd "
+if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then
+ echo Found kernel image: ${kernel_file};
+ if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \
+ ${kernel_file}; then
+ run mmcargs;
+ run boot_fitImage;
+ fi;
+fi;"
+
+#------------------------------------------------------------
+#
+# Provide 'boot_tftp_kernel' command
+#------------------------------------------------------------
+setenv download_kernel "tftpboot ${loadaddr} ${kernel_file}"
+
+setenv boot_tftp_kernel "
+if run download_kernel; then
+ run mmcargs;
+ run boot_fitImage;
+fi"
+
+#------------------------------------------------------------
+#
+# Provide 'boot_nfs' command
+#------------------------------------------------------------
+setenv rootpath "/srv/tftp/KP/rootfs"
+setenv nfsargs "setenv bootargs root=/dev/nfs rw \
+ nfsroot=${serverip}:${rootpath},nolock,nfsvers=3"
+setenv addip "setenv bootargs ${bootargs} \
+ ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:\
+ ${hostname}:eth0:on"
+
+setenv boot_nfs "
+if run download_kernel; then
+ run nfsargs;
+ run addip;
+ setenv bootargs ${bootargs} console=${console};
+
+ run boot_fitImage;
+fi"
+
+#------------------------------------------------------------
+#
+# Set correct boot flow
+#------------------------------------------------------------
+
+setenv bcmd "
+if test ! -n ${bootcmd_force}; then
+ run bootcmd;
+fi;
+if test ${bootcmd_force} = nfs; then
+ run boot_nfs;
+else if test ${bootcmd_force} = tftp_kernel; then
+ run boot_tftp_kernel;
+ fi;
+fi"
+
+run bcmd
diff --git a/board/k+p/kp_imx6q_tpc/Kconfig b/board/k+p/kp_imx6q_tpc/Kconfig
new file mode 100644
index 0000000000..62e34978ec
--- /dev/null
+++ b/board/k+p/kp_imx6q_tpc/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KP_IMX6Q_TPC
+
+config SYS_BOARD
+ default "kp_imx6q_tpc"
+
+config SYS_VENDOR
+ default "k+p"
+
+config SYS_CONFIG_NAME
+ default "kp_imx6q_tpc"
+
+endif
diff --git a/board/k+p/kp_imx6q_tpc/MAINTAINERS b/board/k+p/kp_imx6q_tpc/MAINTAINERS
new file mode 100644
index 0000000000..6c4c8dd28e
--- /dev/null
+++ b/board/k+p/kp_imx6q_tpc/MAINTAINERS
@@ -0,0 +1,6 @@
+KP_IMX6Q_TPC BOARD
+M: Lukasz Majewski <lukma@denx.de>
+S: Maintained
+F: board/k+p/kp_imx6q_tpc/
+F: include/configs/kp_imx6q_tpc.h
+F: configs/kp_imx6q_tpc_defconfig
diff --git a/board/k+p/kp_imx6q_tpc/Makefile b/board/k+p/kp_imx6q_tpc/Makefile
new file mode 100644
index 0000000000..51cbd3e843
--- /dev/null
+++ b/board/k+p/kp_imx6q_tpc/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := kp_imx6q_tpc_spl.o
+else
+obj-y := kp_imx6q_tpc.o
+endif
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
new file mode 100644
index 0000000000..9a5b88029f
--- /dev/null
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
@@ -0,0 +1,302 @@
+/*
+ * K+P iMX6Q KP_IMX6Q_TPC board configuration
+ *
+ * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <errno.h>
+#include <fsl_esdhc.h>
+#include <fuse.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ENET_PAD_CTRL \
+ (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL \
+ (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ /* AR8031 PHY Reset */
+ IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eth_phy_reset(void)
+{
+ /* Reset AR8031 PHY */
+ gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
+ mdelay(10);
+ gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+ udelay(100);
+}
+
+static int setup_fec_clock(void)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* set gpr1[21] to select anatop clock */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
+
+ return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+ setup_fec_clock();
+ eth_phy_reset();
+
+ return cpu_eth_init(bis);
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 output a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ ar8031_phy_fixup(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+ { USDHC2_BASE_ADDR },
+ { USDHC4_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ return !gpio_get_value(USDHC2_CD_GPIO);
+ case USDHC4_BASE_ADDR:
+ return 1; /* eMMC/uSDHC4 is always present */
+ }
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 micro SD
+ * mmc2 eMMC
+ */
+ gpio_direction_input(USDHC2_CD_GPIO);
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+ /*
+ * Set daisy chain for otg_pin_id on MX6Q.
+ * For MX6DL, this bit is reserved.
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return USB_INIT_DEVICE;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ break;
+ case 1:
+ gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /* Enable eim_slow clocks */
+ setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ /* 8 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ env_set("boardname", "kp-tpc");
+ env_set("boardsoc", "imx6q");
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
+ return 0;
+}
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
new file mode 100644
index 0000000000..3fdfea7546
--- /dev/null
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
@@ -0,0 +1,338 @@
+/*
+ * K+P iMX6Q KP_IMX6Q_TPC board configuration
+ *
+ * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <fuse.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+
+#define UART_PAD_CTRL \
+ (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL \
+ (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+/* onboard microSD */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+/* eMMC */
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+/* SD */
+static void setup_iomux_sd(void)
+{
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+/* UART */
+static iomux_v3_cfg_t const uart1_pads[] = {
+ IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart1_pads);
+}
+
+/* USB */
+static iomux_v3_cfg_t const usb_pads[] = {
+ IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_usb(void)
+{
+ SETUP_IOMUX_PADS(usb_pads);
+}
+
+/* DDR3 */
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdclk_1 = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_reset = 0x00000030,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x00000030,
+ .dram_sdodt1 = 0x00000030,
+
+ .dram_sdqs0 = 0x00000018,
+ .dram_sdqs1 = 0x00000018,
+ .dram_sdqs2 = 0x00000018,
+ .dram_sdqs3 = 0x00000018,
+ .dram_sdqs4 = 0x00000018,
+ .dram_sdqs5 = 0x00000018,
+ .dram_sdqs6 = 0x00000018,
+ .dram_sdqs7 = 0x00000018,
+
+ .dram_dqm0 = 0x00000018,
+ .dram_dqm1 = 0x00000018,
+ .dram_dqm2 = 0x00000018,
+ .dram_dqm3 = 0x00000018,
+ .dram_dqm4 = 0x00000018,
+ .dram_dqm5 = 0x00000018,
+ .dram_dqm6 = 0x00000018,
+ .dram_dqm7 = 0x00000018,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000018,
+ .grp_b1ds = 0x00000018,
+ .grp_b2ds = 0x00000018,
+ .grp_b3ds = 0x00000018,
+ .grp_b4ds = 0x00000018,
+ .grp_b5ds = 0x00000018,
+ .grp_b6ds = 0x00000018,
+ .grp_b7ds = 0x00000018,
+};
+
+static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001F001F,
+ .p0_mpwldectrl1 = 0x001F001F,
+ .p1_mpwldectrl0 = 0x001F001F,
+ .p1_mpwldectrl1 = 0x001F001F,
+ .p0_mpdgctrl0 = 0x43270338,
+ .p0_mpdgctrl1 = 0x03200314,
+ .p1_mpdgctrl0 = 0x431A032F,
+ .p1_mpdgctrl1 = 0x03200263,
+ .p0_mprddlctl = 0x4B434748,
+ .p1_mprddlctl = 0x4445404C,
+ .p0_mpwrdlctl = 0x38444542,
+ .p1_mpwrdlctl = 0x4935493A,
+};
+
+/* MT41K256M16 (4Gb density) */
+static const struct mx6_ddr3_cfg mt41k256m16 = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+#ifdef CONFIG_MX6_DDRCAL
+static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+ struct mx6_mmdc_calibration calibration = {0};
+
+ mmdc_read_calibration(sysinfo, &calibration);
+
+ debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
+ debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
+ debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
+ debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
+ debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
+ debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
+ debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
+ debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
+ debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
+ debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
+ debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
+ debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
+}
+
+static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
+{
+ int ret;
+
+ /* Perform DDR DRAM calibration */
+ udelay(100);
+ ret = mmdc_do_write_level_calibration(sysinfo);
+ if (ret) {
+ printf("DDR: Write level calibration error [%d]\n", ret);
+ return;
+ }
+
+ ret = mmdc_do_dqs_calibration(sysinfo);
+ if (ret) {
+ printf("DDR: DQS calibration error [%d]\n", ret);
+ return;
+ }
+
+ spl_dram_print_cal(sysinfo);
+}
+#endif /* CONFIG_MX6_DDRCAL */
+
+static void spl_dram_init(void)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ /* width of data bus:0=16,1=32,2=64 */
+ .dsize = 2,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
+ .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .pd_fast_exit = 1, /* enable precharge power-down fast exit */
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 1, /* Refresh cycles at 32KHz */
+ .refr = 7, /* 8 refresh commands per refresh cycle */
+ };
+
+ mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
+
+#ifdef CONFIG_MX6_DDRCAL
+ spl_dram_perform_cal(&sysinfo);
+#endif
+}
+
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bd)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned int reg = readl(&psrc->sbmr1) >> 11;
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x1 SD1
+ * 0x3 SD4
+ */
+
+ switch (reg & 0x3) {
+ case 0x1:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x3:
+ SETUP_IOMUX_PADS(usdhc4_pads);
+ usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ }
+
+ return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* setup GP timer */
+ timer_init();
+
+ setup_iomux_sd();
+ setup_iomux_uart();
+ setup_iomux_usb();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index ee9e4f7c01..727b639943 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -428,7 +428,7 @@ static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
.dram_ras = 0x00020030,
- .dram_reset = 0x00020030,
+ .dram_reset = 0x000c0030,
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
.dram_sdba2 = 0x00000000,
@@ -584,7 +584,6 @@ static struct mx6_ddr3_cfg mem_ddr_2g = {
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
- .SRT = 1,
};
static struct mx6_ddr3_cfg mem_ddr_4g = {
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 1e7c11e670..b7c6c6cb18 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -28,7 +28,6 @@
#include <miiphy.h>
#include <netdev.h>
#include <phy.h>
-#include <input.h>
#include <i2c.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
index d422d63df5..327f656c44 100644
--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -23,6 +23,8 @@
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../freescale/common/pfuze.h"
+#include <asm/setup.h>
+#include <asm/bootm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -186,6 +188,10 @@ int board_usb_phy_mode(int port)
int board_late_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+#ifdef CONFIG_SERIAL_TAG
+ struct tag_serialnr serialnr;
+ char serial_string[0x20];
+#endif
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
@@ -197,5 +203,13 @@ int board_late_init(void)
*/
clrsetbits_le16(&wdog->wcr, 0, 0x10);
+#ifdef CONFIG_SERIAL_TAG
+ /* Set serial# standard environment variable based on OTP settings */
+ get_board_serial(&serialnr);
+ snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x",
+ serialnr.low, serialnr.high);
+ env_set("serial#", serial_string);
+#endif
+
return 0;
}